Sohiful Anuar Zainol Murad
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Preferred name
Sohiful Anuar Zainol Murad
Official Name
Sohiful Anuar, Zainol Murad
Alternative Name
Murad, S. A.Zainol
Murad, S. A.Zainol
Anuar, Zainol Murad Sohiful
Zainol Murad, S.A.
Sohiful, Z. M.A.
Main Affiliation
Scopus Author ID
16643180100
Researcher ID
I-1082-2019

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Single wall carbon nanotubes dispersion study of different dye molecules and chitosan

2017-09-26 , Muhammad Mahyiddin Ramli , Siti Salwa Mat Isa , Mohd. Mustafa Al Bakri Abdullah , Sohiful Anuar Zainol Murad

Carbon Nanotubes (CNTs) is known for their hydrophobicity ability. However, this ability can become the bottleneck for the application of CNTs where a highly dispersion of materials are needed. In this project, different dispersing agents were investigated namely dye molecules and chitosan. Three different dyes are studied with different concentration, including 0.05 % of chitosan. The dispersion quality is determined by examining through UV-Vis-NIR. The best dispersion quality investigated here is when the concentration of dye molecules is higher, which is around 2.5 mM.

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Electrical conductivity (EC) sensing system for paddy plant using the internet of things (IoT) connectivity

2020-01-08 , Othaman N.N.C. , Mohd Nazrin Md Isa , Sohiful Anuar Zainol Murad , Azizi Harun , Shaiful Nizam Mohyar

This paper presents the design and development of an IoT-based electrical conductivity system for measuring paddy soil nutrients. Relationship between electrical conductivity (EC) and the influence of soil temperature in precision farming will be discussed. In this work, the EC algorithm was modelled and verified using MATLAB and realized on Node MCU (ESP8266) microcontroller. Results showed that the measured data from the developed system is closed to the calibration solution conductivity that is 1.413mS/cm and 12.88mS/cm. It is also noted that the recorded electrical conductivity value increases with temperature.

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Design of a 24.5 GHZ CMOS low noise amplifier using 0.13-µM technology for 6G wireless applications

2025-11-11 , Sohiful Anuar Zainol Murad , Asrulnizam Abd Manaf , Nuha A. Rhaffor , Ruhaifi Abdullah Zawawi

The need for high-performance circuit designs is growing as wireless communication technologies continue to advance and support newer generations of wireless applications. Much emphasis has been focused on the possibility of the 24 GHz frequency band in next-generation wireless networks, including 5G and beyond. Designing a low noise amplifier (LNA) operating at 24 GHz presents several challenges. The primary concerns include achieving high gain, low power consumption, low noise figure, and while maintaining good linearity and stability. This paper presents the design, simulation, and layout of a CMOS LNA optimized for operation at 24.5 GHz frequency, targeting 6G and beyond wireless communication applications. The proposed LNA employs three stages with a cascode topology at the first stage and follow by a common source stage at second and third stage. The three stages help to achieve high gain, and the source degeneration inductor at the first stage helps to improve linearity. Extensive simulations were conducted using a 0.13-µm CMOS technology, demonstrating a peak gain of 21 dB and a noise figure of 5.6 dB at 24.5 GHz. The LNA also exhibits good linearity and stability over a wide bandwidth. The performance metrics were validated through simulation and comparison, showcasing the feasibility of the designed LNA for 6G applications. This work contributes to the advancement of CMOS-based radio frequency (RF) front-end designs for next-generation wireless communication systems.

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Optimizing the Output Voltage of Piezoelectric Energy Harvesting with DC-DC Booster Circuit

2023-01-01 , Bin Sahijin I.A. , Karim J. , Sohiful Anuar Zainol Murad

A vibration-based low-voltage DC-DC boost converter is presented in this research. Powering a gadget with less than 1V energy needs a boost circuit, a switching gate boost converter was utilized to enhance the input voltage for low vibration frequency. To determine the optimal duty cycle, inductance, and load capacitance for a booster circuit, L Tspice XVII software was used with input less than 1 V. The output voltage range from 26V to 61 V increases linearly with the input voltage range from O.3V to O.7V.The best parameters for a 10k load are a 50uH inductor and a 10uF load capacitor. The voltage converter is suitable for vibration energy harvesting in automotive, healthcare, and wireless sensor network applications with low input voltage and low frequency in the KHz range

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UWB CMOS low noise amplifier for mode 1

2017-07-02 , Tun Zainal Azni Zulkifli , Arjuna Marzuki , Sohiful Anuar Zainol Murad

This paper presents an ultra-wideband 3.1-4.9 GHz low noise amplifier (LNA) employing a sixth-order bandpass Chebyshev filter. The LNA has been designed using Silterra 0.18 μm CMOS technology at 1.8 V power supply. The simulation shows that the LNA attains a power gain of 14.1 dB with an input reflection coefficient less than -10 dB in frequency range of interest, a noise figure of 4.29 dB at 3.8 GHz, gain flatness of ±0.25 dB, a 1 dB compression point of -17.67 dBm, -6.90 dBm for IIP3 and power dissipation of 4.5 mW excluding the buffer stage.

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Ultra-Low Power 0.55 mW 2.4 GHz CMOS Low-Noise Amplifier for Wireless Sensor Network

2022-01-01 , Sohiful Anuar Zainol Murad , Azizan A. , Sapawi R. , Zulkifli T.Z.A.

This paper describes the design topology of two-stage ultra-low power low noise amplifier (LNA) using the forward body bias technique for wireless sensor network (WSN) application. The proposed design employs CMOS 0.13-µm technology at 2.4 GHz frequency. The LNA consumes low power from the forward body bias technique at the first and the second stages. The threshold voltage of the transistor can be lowered using the forward body bias technique. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The measurement results show that the LNA consumes a total power of 0.55 mW at supply voltage 0.55 V. The input return loss (S11) and the output return loss (S22) is 10 and 12 dB, respectively. A gain of 12 dB, noise figure (NF) of 5.9 dB and input third-order intercept point (IIP3) of −3 dBm are achieved.

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Design of High-Quality Factor Active Indictor Using CMOS 0.18-μm Technology for 5G Applications

2022-01-01 , Ali H.A.A.A. , Sohiful Anuar Zainol Murad , Ahmad Fariz Hasan , Faizah Abu Bakar , Sapawi R.

This paper presents high quality factor of active inductor circuit for 5G application. The proposed circuit is based on the differential active inductor (DAI) topology. The DAI is designed using CMOS 0.18 μm technology. The quality factor (Q) can be tuned with the current source values, ranging from 0.5 mA to 3 mA, while the voltage can control the inductance values L. Meanwhile, the frequency range can be controlled with the feedback resistance. The simulation results indicate that the Q factor as large as 262.5k can be achieved with inductor values of 10 nH at frequency 3.2 GHz. In addition, the Q factor of 1650 is obtained at 3.5 GHz. The performance comparison with previously published works is also demonstrated and found that the proposed DAI is suitable for 5G application.

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Machine vision for laser defect in PV solar modules

2016 , R. Shuaimi , Rizalafande Che Ismail , Mohd Nazrin Md Isa , Sohiful Anuar Zainol Murad

This paper presents a new methodology in inspection on laser scribe defect of PV thin film solar modules. The work focuses on the application of machine vision as an inspection tools which has successfully integrated in other manufacturing environment as pattern recognition utility. Compared to manual inspection by human, machine vision system could offer better measurement accuracy as scribe defects are extremely hard to detect due to their small sizes and complexity of the detection process. Studies were made to identify machine vision system screening capabilities to define different scribe defect by their inspection criteria. Current result with paper and broad samples indicates that the propose system can be used effectively to replace human evaluators that currently employs in manufacturing quality control. © 2016 IEEE.

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Design and characterization of a 3.5 GHz CMOS power amplifier for low-band 5G applications

2025 , Ahmad Fariz Hasan , Sohiful Anuar Zainol Murad , Faizah Abu Bakar , Rohana Sapawi

A 3.5 GHz CMOS power amplifier (PA) designed for 5G applications is presented in this study, utilizing the 0.18 µm RF CMOS process technology. The circuit architecture comprises two stages: the first stage employs a cascode topology with a negative voltage applied to the transistor body technique to achieve sufficient gain and minimize current, thereby reducing power consumption. In the second stage, to ensure high efficiency, a class-E amplifier is being used. Measurement results indicate a power gain (S21) of 17.2 dB, a power-added efficiency (PAE) of 45.6% and a saturated power (Psat) of 8.5 dBm, obtained at 3.5 GHz. These findings validate the suitability of the proposed design at low-band frequency for 5G applications. The chip area for the proposed design is 2.45 mm². The discrepancy between simulation and measurement is due to the parasitic in the layout design.

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Modelling on Impact of Building Obstruction for V2I Communication Link in Micro Cellular Environment

2021-03-01 , Turner J.S.C. , Shahriman Abu Bakar , Azizi Harun , Sohiful Anuar Zainol Murad , Isa M.N. , Ismail R.C. , Ndzi D.L. , Hashim M.S.M. , Zuradzman Mohamad Razlan , Wan Khairunizam Wan Ahmad , Ramli M.F.

In vehicular communication, signal transmission in vehicle-to-infrastructure (V2I) mode typically takes place on highways, urban, suburban and rural environments. The presence of buildings in these environments poses a challenge to model path loss (PL) due to multiple propagation mechanisms such as diffractions and reflections. However, very little attention has been made to address building effects on the performance of V2I communication links in microcell environment. This paper investigates signal propagation characteristics caused by the impact of building under micro-cellular environment whereby the base station or road-side-unit (RSU) is usually located under the rooftop of building to allow communication between RSU and mobile station or on-board-unit (OBU) on the road. The goal of this paper is to validate and discuss available path loss models based on effect of building obstruction towards RSU-OBU links specifically in residential housing area. The channel measurements are conducted based on static line-of-sight (LOS) settings of a real-world environment at 2.4 GHz frequency band using IEEE 802.15.4 XBee S2C compliant device to measure its receive power. The results are demonstrated based on received signal strength indicator (RSSI) and root mean square error (RMSE). The attenuation profile is validated and compared with suitable path loss models to evaluate best fit and most compatible model based on our measurements data and environment. The analysis shows that several V2I path loss models and V2V channel models are applicable to be used as a reference to model in LOS microcell environment with building obstruction. The finding shows that PL Urban yields the best fit V2I path loss model in terms of RMSE when compared to our measurement campaign at 2.4 GHz.

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