Mohd Nazri Mohd Warip
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Preferred name
Mohd Nazri Mohd Warip
Official Name
Mohd Nazri , Mohd Warip
Alternative Name
Mohd Warip, Mohd Nazri
Mohd Warip, M. N.
Warip, M. N.
Warip, Mohd Nazri Mohd
Warip, Mohd Nazri bin Mohd
Main Affiliation
Scopus Author ID
36555091900
Researcher ID
EDT-8958-2022

Research Output

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The impact of inner-parameters B-MAC protocol by Taguchi method for WSN

2020-03-15 , Yousif A.K. , Mohd Nazri Mohd Warip , Mohamed Elshaikh Elobaid Said Ahmed

The MAC protocols play an important role in the performance of wireless sensor network (WSN). MAC protocols are controlled with set of parameters from being dragged to undesired situation such as reduce the power consumption, listening idle, and overhead. This inner- parameters have direct impact on the efficiency of a MAC protocols and overall network performances. The impacts of theses parameters on reduce the power consumption are less considered. In the literature, a lot of studies concentrates on introducing a new protocols to reduce the power consumption for WSN. This paper aims to analysis the inner- parameters of MAC protocols for WSN power consumption by using Taguchi Delta Analysis (TDA). Moreover, the measure of inner - parameters is very important to find the optimal values to reduce the power consumption. This paper utilized Taguchi method to analysis the impact of B-MAC protocol parameters in WSN scenarios by exploits Taguchi delta analysis. Further, four inner - parameters are investigated in a simulation platform. Moreover, simulation experiments are carried out by OMNET++5 to prove the work in this paper. The obtained results show that inner- parameters B-MAC inner- protocol reduce the power consumption of WSN for two different scenarios.

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Hyper-threading technology: Not a good choice for speeding up CPU-bound code

2017-01-03 , Ng Hui Qun , Zahereel Ishwar Abdul Khalib , Mohd Nazri Mohd Warip , Mohamed Elshaikh Elobaid Said Ahmed , Mostafijur R. , Nik Adilah Hanin Zahri , Puteh Saad

Hyper-threading (HT) technology allows one thread to execute its task while another thread is stalled waiting for shared resource or other operations to complete. Thus, this reduces the idle time of a processor. If HT is enabled, an operating system would see two logical cores per each physical core. This gives one physical core the ability to run two threads simultaneously. However, it does not necessarily speed up the performance of a parallel code twice the number of physical cores. This happens when two threads are trying to access the shared CPU resource. The instructions could only be executed one after another at any given time. In this case, parallel CPU-bound code could attain a little improvement in terms of speedup from HT on a quad-core platform, which is Intel i5-2410M@2.30GHz.

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Comparative Study of Parallelism and Pipelining of RGB to HSL Colour Space Conversion Architecture on FPGA

2020-03-20 , Pakhlen Ehkan , Siew, Soon Voon , Fazrul Faiz Zakaria , Mohd Nazri Mohd Warip , Mohd Zaizu Ilyas

RGB colour model is a basic colour model and complements together to produce full colour range but it is unable to produce sufficient information for digital image analysis. However, HSL is capable to provide other useful information such as colour in degree, saturation of the colour and brightness of colour. In this work, RGB to HSL mathematical conversion algorithm is implemented on FPGA chip. Parallelism and pipelining capabilities of FPGA helps to speed up conversion performance. The RGB to HSL equation is implemented by using two architectures which are parallel and 7-stages pipeline architectures. The designed parallel and pipeline converters have one clock and seven clock cycle of data latency respectively. The parallel and pipeline architectures for RGB to HSL converter have been achieved rate of accuracy by hardware verification up to 99% and 98% and possessed maximum operating frequency merit of 50 MHz and 120 MHz respectively.

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Breast cancer classification using deep learning and FPGA inferencing

2023-02-21 , Wong E.H. , Fazrul Faiz Zakaria , Mustapa M. , Mohd Nazri Mohd Warip , Phak Len Al Eh Kan

Implementing deep learning technology with FPGA as an accelerator has become a popular application due to its efficiency and performance. However, given the tremendous data generated on medical diagnosis, normal inference speed is not sufficient. Hence, the FPGA technology is implemented for fast inference. In this context, the FPGA accelerates the deep learning inference process for fast breast cancer classification with minimal latency on real-time deployment. This paper summarizes the findings of model deployment across various computing devices in deep learning technology with FPGA. The study includes model performance evaluation, throughput, and latency comparison with different batch sizes to the extent of expected delay for real-world deployment. The result concludes that FPGA is the most suitable to act as a deep learning inference accelerator with a high throughput-to-latency ratio and fast parallel inference.

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Comparing and Assessing the Enhancements of DYMO and OLSR in VANETs

2020-09-21 , Khalid Ahmed W. , Mohd Nazri Mohd Warip , Khalid Abduljabbar W. , Mohamed Elshaikh Elobaid Said Ahmed

The main aspect of this work is to study the differences and define the behaviour of two different routing protocols. The first side is Dynamic MANETs On- Demand (DYMO) while the other side is proactive, optimal link-state routing (OLSR) and both the first and second are interactive routing protocols in the Ad-hoc network (VANET). The efficiency of these protocols was analysed and studied based on the use of three performance indicators: PDR, normal load (NRO) and end-to-end de1ay (E2ED) on the ability to change the size of different nodes. Omnet ++ was used by the INET Framework. We also used the SUMO simulation tool to build random movement patterns for VANET. From full simulation, we noticed that OLSR is doing better than DYMO for VANET at a price. Late and, as a result, the development of OLSR work in VANETs compared to DYMO, packet receipt ratios (PDR), side-to-side delay, normal path load, and VANETs.

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Multipoint Relay Path for Efficient Topology Maintenance Algorithm in Optimized Link State Routing-Based for VANET

2024-01-01 , Waleed Khalid Ahmed , Mohd Nazri Mohd Warip , Mohamed Elshaikh Elobaid Said Ahmed , Phak Len Al Eh Kan

The Optimal Link State Routing (OLSR) protocol employs multipoint relay (MPR) nodes to disseminate topology control (TC) messages, enabling network topology discovery and maintenance. However, this approach increases control overhead and leads to wasted network bandwidth in stable topology scenarios due to fixed flooding periods. To address these challenges, this paper presents an Efficient Topology Maintenance Algorithm (ETM-OLSR) for Enhanced Link-State Routing Protocols. By reducing the number of MPR nodes, TC message generation and forwarding frequency are minimized. Furthermore, the algorithm selects a smaller subset of TC messages based on the changes in the MPR selection set from the previous cycle, adapting to stable and fluctuating network conditions. Additionally, the sending cycle of TC messages is dynamically adjusted in response to network topology changes. Simulation results demonstrate that the ETM-OLSR algorithm effectively reduces network control overhead, minimizes end-to-end delay, and improves network throughput compared to traditional OLSR and HTR-OLSR algorithms.

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Imporved MPR selection algorithm-based WS-OLSR routing protocol

2024-05-01 , Ahmed W.K. , Mohd Nazri Mohd Warip , Mohamed Elshaikh Elobaid Said Ahmed , Phak Len Al Eh Kan

Vehicle Ad Hoc Networks (VANETs) have become a viable technology to improve traffic flow and safety on the roads. Due to its effectiveness and scalability, the Wingsuit Search-based Optimised Link State Routing Protocol (WS-OLSR) is frequently used for data distribution in VANETs. However, the selection of MultiPoint Relays (MPRs) plays a pivotal role in WS-OLSR’s performance. This paper presents an improved MPR selection algorithm tailored to WS-OLSR, designed to enhance the overall routing efficiency and reduce overhead. The analysis found that the current OLSR protocol has problems such as redundancy of HELLO and TC message packets or failure to update routing information in time, so a WS-OLSR routing protocol based on improved-MPR selection algorithm was proposed. Firstly, factors such as node mobility and link changes are comprehensively considered to reflect network topology changes, and the broadcast cycle of node HELLO messages is controlled through topology changes. Secondly, a new MPR selection algorithm is proposed, considering link stability issues and nodes. Finally, evaluate its effectiveness in terms of packet delivery ratio, end-to-end delay, and control message overhead. Simulation results demonstrate the superior performance of our improved MR selection algorithm when compared to traditional approaches.

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Perceptual-based features for blind image quality assessment using extreme learning machine for biodiversity monitoring

2024-02-08 , Verak N. , Pakhlen Ehkan , Ruzelita Ngadiran , Jungjit S. , Fazrul Faiz Zakaria , Mohd Nazri Mohd Warip , Ilyas M.Z.

Blind Image Quality Assessment (BIQA) is crucial for various image processing applications, including image denoising, transmission evaluation, optimization, watermarking, and situations where a reference image is unavailable. However, existing state-of-the-art Image Quality Assessment (IQA) metrics are often specific to certain types of distortion and fail to align with human perception. To address this issue, our research study proposes a novel approach that incorporates perceptual-based features and utilizes a pooling algorithm based on Extreme Learning Machine (ELM). By considering human visual characteristics and the impact on image content, we aim to mimic human perception, which can detect noticeable differences at specific frequency ranges, akin to neurons. The work is divided into three phases. In the first phase, we derive perceptual features using lifting wavelet, focusing on texture, edge, and contrast components. Subsequently, in the second phase, these features are trained to generate output for pooling using Extreme Learning Machine (ELM). The pooling strategy of ELM is chosen due to its ability to overcome limitations found in previous pooling techniques like Neural Networks (NNs) and Support Vector Regression (SVR). This approach enables us to evaluate the quality score of images accurately, benefiting from ELM's superior learning accuracy and faster learning speed. The third phase involves performance evaluation, including statistical analysis for algorithm validation and a comparison with existing BIQA methods using MATLAB software. We verify our proposed approach on diverse image databases containing various distortion types, aiming to create a general-purpose BIQA solution. The outcomes of this work will have significant implications in several image processing applications, such as optimizing image enhancement for medical purposes like tumor or cancer detection, image watermarking for security applications, image coding and compression, and image forensic analysis. In biodiversity monitoring, image enhancement plays a crucial role in tracking and data collection.

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Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

2017-06-01 , Ng Yen Phing , Mohd Nazri Mohd Warip , Phak Len Al Eh Kan , Farah W. Zulkefli , R Badlishah Ahmad

In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as a design solution to System-on-Chip (SoC). The routing algorithm, topology and switching technique are significant because of the most influential effect on the overall performance of Network-on-Chip (NoC). Designing of large scale topology alongside the support of deadlock free, low latency, high throughput and low power consumption is notably challenging in particular with expanding network size. This paper proposed an 8x8 XX-Torus and 64 nodes XX-Ring topology schemes for Network-on-Chip to minimize the latency by decrease the node diameter from the source node to destination node. Correspondingly, we compare in differences on the performance of mesh, full-mesh, torus and ring topologies with XX-Torus and XX-Ring topologies in term of latency. Results show that XX-Ring outperforms the conventional topologies in term of latency. XX-Ring decreases the average latency by 106.28%, 14.80%, 6.7 1%, 1.73%, 442.24% over the mesh, fully-mesh, torus, XX-torus, and Ring topologies.

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Deep-Learning Assisting Cerebral Palsy Patient Handgrip Task Translation

2021-07-26 , Fazrul Faiz Zakaria , Mohd Nazri Mohd Warip , Phaklen Ehkan , Muslim Mustapa , Mohd Zaizu Ilyas

An electro-encephalography (EEG) brain-computer interface (BCI) can provide the brain and external environment with separate information sharing and control networks. EEG impulses, though, come from many electrodes, which produce different characteristics, and how the electrodes and features to enhance classification efficiency have been chosen has become an urgent concern. This paper explores the deep convolutional neural network architecture (CNN) hyper-parameters with separating temporal and spatial filters without any pre-processing or artificial extraction processes. It selects the raw EEG signal of electrode pairs over the cortical area as hybrid samples. Our proposed deep-learning model outperforms other neural network models previously applied to this dataset in training time (∼40%) and accuracy (∼6%). Besides, considerations such as optimum order for EEG channels do not limit our model, and it is patient-invariant. The impact of network architecture on decoder output and training time is further discussed.

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