Mohd Nazrin Md Isa
Thumbnail Image
Preferred name
Mohd Nazrin Md Isa
Official Name
Mohd Nazrin , Md Isa
Alternative Name
Md Isa, Mohd N.
Isa, M. Nazrin Md
Md Isa, M. N.
Isa, Nazrin
Isa, M. Nazrin M.
Main Affiliation
Scopus Author ID
56426995200
Researcher ID
N-1250-2017

Research Output

Filters

4 1
1
4
4
Reset filters

Settings
Now showing 1 - 4 of 4
Thumbnail Image
Publication

An implementation of Short Time Fourier Transform for Harmonic Signal Detection

2021-03-01 , Basir M.S.S.M. , Rizalafande Che Ismail , Yusof K.H. , Katim N.I.A. , Mohd Nazrin Md Isa , Siti Zarina Md Naziri

Power electronic components has the tendency to induce a non-linear signal called harmonic distortion. Without proper monitoring tools, harmonic distortion can harm sensitive electronic equipment, and in worse case scenarios, may lead to unreliable operation of controller and misalignment of motoring unit. This matter can be compromised by taking safety precaution, by identifying the level of harmonic rise in the electrical system. This paper presents analysis on different characteristics of harmonic signal using frequency distribution technique, namely Fourier transform (FT), and proposal of time-frequency distribution (TFD) technique, which is a short time Fourier transform (STFT). The novelty of utilizing STFT is the analyzed signal is represented in both time and frequency marginals, hence providing extra information of the spectral over the time. Simulation was carried out using MATLAB, by means the results consisting of the magnitude of multi-frequency components signal were represented in time-frequency representation (TFR). From the TFR, parameters such as instantaneous RMS fundamental voltage, V1RMS(t), instantaneous RMS voltage, VRMS(t), instantaneous total waveform distortion, VTWD(t), instantaneous total harmonic distortion, VTHD(t) and instantaneous total nonharmonic distortion, VTnHD(t) had been extracted. The performance of different harmonic signals such as normal, single-level harmonic, multi-level harmonic, short duration harmonic and interharmonic had been analyzed. The performance based on absolute percentage error (APE) index indicated average of 93% of correctness using 256 window length in STFT measurement.

View
Thumbnail Image
Publication

Speed and Area Efficient FXP Adders and Multipliers: A Comparative Analysis for LNS System

2020-12-18 , Basir M.S.S.M. , Rizalafande Che Ismail , Siti Zarina Md Naziri , Mohd Nazrin Md Isa , Sohiful Anuar Zainol Murad , Azizi Harun

In this paper, a variety of adder and multiplier are compared to be implemented in a new logarithmic number system (LNS). Both adder and multiplier are designed with a generic very high-speed integrated circuit hardware description language (Verilog) program. This makes it possible to achieve the optimum performance in latency and area of 0.18µm CMOS technologies LNS chip. Consequently, the optimal configurations vary with speed and area of the schemes and in some cases can be compact area, O(n), fast in latency O(log2 n) or optimized. The program was scripted based on fixed-point (FXP) adders and multipliers that yet will be implemented in LNS system. The functionality of the scheme was tested before synthesized. Outcomes show that Ladner Fisher (LF) adder and modified Baugh Wooley multiplier contribute to fast in latency and consume minimal area.

View
Thumbnail Image
Publication

Crypto-Core Design using Camellia Cipher

2021-03-01 , Wei Ci C. , Siti Zarina Md Naziri , Rizalafande Che Ismail , Razaidi Hussin , Mohd Nazrin Md Isa , Basir M.S.S.M.

Camellia cipher is another symmetric block cipher which allows the encryption and decryption process to share the same key. The cipher permits a 128-bits input data with three different key size: 128, 192 and 256 bits. This paper presents two hardware design approach of Camellia cipher, which are FPGA and custom-based design approach. These approaches utilized design softwares of Altera Quartus II with device family of Cyclone II and Synopsys Design Compiler. The performance of Camellia crypto-core design is then been evaluated based on the implementation platform in terms of speed, area and power. With an equal base of 50MHz of clock frequency, custom-based design is found more efficient than FPGA-based design due to the execution time achieved with 8.46ns, which is faster than the latter that consumed double the time with 16.075ns. The custom-based design achieved 15.13 Gbps of throughput. Besides, the power consumption of custom-based design is 1.3519 mW which is lower than the FPGA-based design. In a nutshell, the design has successfully done as it achieved expected encryption and decryption outcomes with acceptable performance.

View
Thumbnail Image
Publication

A Novel Double Co-Transformation for a Simple and Memory Efficient Logarithmic Number System

2020-07-01 , Basir M.S.S.M. , Rizalafande Che Ismail , Mohd Nazrin Md Isa

To date, co-transformation architecture is typically used in resolving the singularity issue in the logarithmic number system (LNS). The co-transformation was first introduced by Coleman, by using a rule of sign(r1) ≠ sign(r2) which translate the singularity into an argument that can be stored in two identical look-up tables (LUTs) with size of 2k. Recently, a portable 32-bit chipset preferred a small LUT, hitherto a co-transformation architecture is rearranged. This paper presents a novel double co-transformation, by means of first-order co-transformation architecture that covers-0.5 < r < 0 region is extended to r >-1 to replace the triumvirate F, D and E tables occupy by the interpolator. The accuracy settings at the co-transformation is compromised with the worst case error of 0.5 ulp. The outcome revealed a double co-transformation with Lagrange interpolator shows a decline in the total bit by 13% compared to European Logarithmic Microprocessor (ELM). With a simple architecture, the proposed double co-transformation is a promise for a fast LNS system.

View