Faradilla Aziz
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Faradilla Aziz
Official Name
Faradilla, Aziz
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Simulation and characterization of an inverter logic gate by utilizing InGaAs-based planar devices

2023-12 , Faradilla Aziz , Shahrir Rizal Kasjoo , Nor Farhani Zakaria , Fauzi Packeer , A. K. Singh

Electronic circuits known as logic gates can perform basic logical operations like inverters, AND, and OR gates. These logic gates serve as the basis for digital electronics, and they are a common component in various electronic devices, such as computers, smartphones, and other types of digital systems. This research presents an inverter logic gate made of planar devices, which have significantly simpler structures than multi-layered transistors and diodes, namely the self-switching diode (SSD) and side-gated transistor (SGT). The inverter logic gate is realized by simply connecting both SSD and SGT in parallel. The electrical characteristics and performances of the inverter logic gate are assessed based on InGaAs material using SILVACO Inc.'s ATLAS device simulator software. The simulation results show that the functionality of the proposed planar inverter is comparable to that of a conventional inverter logic gate based on the standard truth table of the device. This has demonstrated the feasibility of building logic gates using a combination of SSDs and SGTs. In addition, the planar structure of SSD and SGT allows for a relatively low-cost device fabrication process as well as offering a high-frequency operation due to low parasitic elements in the devices.

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Simulation of InGaAs-based self-switching diodes as sub-terahertz rectifiers

2022-12 , Faradilla Aziz , Shahrir Rizal Kasjoo , Nor Farhani Zakaria , Fauzi Packeer , A.K. Singh

Abstract. A self-switching device (SSD) is a new device concept -which can be simply realized by forming insulating trenches into a semiconductor layer, using a single nanolithography process. SSDs can be utilized as rectifiers since the device's current-voltage (I-V) characteristic is comparable to that of a conventional diode. The simulation of two InGaAsbased SSDs with parallel connection using ATLAS device simulator for similar and different lengths of both SSDs (L1 and L2) is presented in this paper. The simulation results show that the InGaAs-based SSDs are able to operate up to sub-terahertz (THz) frequencies. As expected, lowering either L1 or L2 will not only increase the device’s cut-off frequency, fc, but also degrading the device’s rectification performance (i.e., reducing the value of curvature coefficient, γ). The highest cut-off frequency achieved in this work was 0.27 THz with γ ~18V-1 when L1 = 0.8 μm and L2 = 0.4 μm.

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Design and analysis of 90 nm two-stage operational amplifier using floating-gate MOSFET

2017 , Faradilla Aziz

Low voltage, low power dissipation, high gain and matching are some of the concern when designing an analog circuit. A very low voltage can increase battery lifetime and integration density as market demands. Floating-gate Metal-Oxide-Semiconductor (MOS) also known as FGMOS is a new technology design that has been introduced as an element in low voltage circuit design in CMOS technology. FGMOS technique has been reported as low voltage and low power design application for increasing the battery lifetime due to its lower threshold voltage. The operational time of the FGMOS transistor can be improved by controlling the threshold voltage without reducing the feature size of the transistor. This research focuses on analyzing and comparing the simulation application of FGMOS technique with conventional MOSFET for various circuit designs. Capacitor ratio of 0.5 with value of 2 fF of the FGMOS transistor is chosen in order to have most stable output result. Proposed FGMOS operational amplifier circuit consists of two stages namely input differential circuit and output buffer stage that contributes in amplifying an input signal. The circuit simulations are analyzed using Full Custom Synopsys software with 90 nm CMOS technology. The simulated results show approximately 42 dB of gain with 3dBbandwidth of 233 kHz, unity gain bandwidth of 23.6 MHz and total power dissipation of 203.3520 mW. In conclusion, the proposed FGMOS designs show comparable result with conventional MOSFET designs. However, the proposed design performance can be improved in further research due to its lower threshold voltage.

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