Theses & Dissertations

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https://hdl.handle.net/20.500.14170/209

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Browsing Theses & Dissertations by Subject "A new concurrent"
  • Publication
    A new concurrent, scalable and modular SoC-FPGA-based architecture for HMLP implementation
    ( 2019)
    Lee Yee Ann
    The hybrid multilayered perceptron (HMLP) is a type of artificial neural network (ANN) that was introduced as an enhancement to the multilayered perceptron (MLP). At the same time, the modified recursive prediction error (MRPE) training algorithm was introduced to train the HMLP. Like other ANNs, the HMLP is comprised of many simple processing nodes that operate independently from other nodes. This property of ANN makes the HMLP a concurrent system. On the other hands, the steps and the equations of the MRPE training algorithm makes the MRPE a sequential system. To date, the HMLP was only implemented on two (2) hardware platforms, but both platforms were sequential microcontrollers, which were unable to fully harness the concurrency of the HMLP. In order to implement both HMLP and MRPE on the same device, devices that combines a concurrent system with a sequential system is the best option. SoC FPGA is a type of semiconductor device that consists of a field-programmable gate array (FPGA) and a system-on-chip (SoC) within the same integrated circuit (IC). The FPGA is able to implement a concurrent system, whereas the SoC can execute a sequential algorithm. Therefore, a new SoC-FPGA-based architecture is proposed to implement the concurrent HMLP and the sequential MRPE on the target Cyclone V SoC on-board the DE1-SoC. The concurrent HMLP is implemented on the FPGA, and the sequential MRPE is executed on the SoC of the target Cyclone V SoC. To implement the HMLP and the MRPE on an SoC FPGA, first, a new concurrent, scalable and modular FPGA-based architecture is developed to implement the HMLP on the FPGA. Second, an FPGA-to-SoC interface module is developed for interfacing the HMLP module on FPGA with the SoC. Third, an MRPE program to execute the MRPE training algorithm on SoC is developed. Lastly, the developed SoC-FPGA-based architecture of HMLP and MRPE is implemented on the target Cyclone V SoC for validation. The developed HMLP implemented on FPGA had been validated to be functioning as expected and exhibiting concurrent, scalable and modular characteristics. The FPGA-to-SoC interface module is found to be able to correctly pass data between the FPGA and the SoC of the target Cyclone V SoC device. The HMLP-MRPE system, that combines the HMLP and the FPGA-to-SoC interface modules on FPGA, and the MRPE training algorithm on SoC, is validated by training the HMLP to learn and deduce the outputs of four-input XOR operation. It is found that the HMLP-MRPE system with ni = 4, nh = 6 and no = 1 is able to correctly deduce the output of a four-input XOR operation. Comparing the output latencies of HMLP with ni = 4, nh = 6 and no = 1 between the SoC FPGA implementation to the MATLAB and SoC-only implementations shows that the concurrent HMLP implemented on SoC FPGA at 50MHz clock can compute its output at 60% of the output latency of HMLP implemented on SoC-only at 800MHz. Additionally, the same HMLP at 100MHz clock is able to compute its output at 50% of the output latency of HMLP implemented on MATLAB, which runs on Intel Core i5 processor at 2.5GHz.