Design and analysis of an efficient repository system for protein coefficients in systolic array-based architecture by using xilinx virtex-5 FPGA

Sequence alignment is a fundamental tool in bioinformatics and computational biology. It aims to search for regions of similarity between biological sequences, which includes DNA, RNA or protein sequences. The search for a newly discovered/unknown (query) sequence and known (subject) sequences from biological databases can be done in either pairwise or multiple sequence alignment. Due to exponential growth of biological database and the time-consuming dynamic programming-based sequence alignment algorithm, researches on FPGA-based accelerators hav e been extensively reported in literature. Typically, performing sequence alignment in hardware requires two stages; configuration and computation stages. These stages have an important role towards producing alignment results in realistic time. In terms of time complexity, the computation stage is the most time consuming part, followed by the configuration stage. The use of systolic array-based architecture in protein sequence alignment has been proven to be one of best and efficient ways to get alignment results in realistic time. However, the configuration stage is still a big challenge especially in the systolic arraybased architecture, thus needs for improvements. Therefore, in this research, an efficient repository system specifically for systolic array-based protein sequence alignment core architecture will be designed to improve performance on the configuration side. Configuration stage involves regular and rapid updates of various protein coefficients in the processing elements (PEs). This is due to the fact that, considerations of biological factors i.e. the probability scores between pairs of amino acids characters (the protein coefficients) or known as substitution matrix is crucial in protein sequence alignment. Typical PE configuration elements used serial configuration chain, whereby each PE in the systolic array architecture will be updated sequentially from the first PE until the last one. Consequently, the PE configuration time will be proportional to the number of PEs, hence increases the overall system configuration time. This research proposes alternative to the existing approach to improve the dependency on the number of PEs and reduce the configuration time. Instead of configuring PE serially, the protein coefficients can be transferred to the PE in parallel from the proposed loader. In this work, a parallel loader for PE configuration has been designed using Verilog HDL. Besides reducing the configuration time, an area optimization of the design has been done by reducing unnecessary substitution matrix columns and rows i.e. from 32 by 32 to only 20 by 20 or 61 percent area reduction. The design core was simulated using Xilinx ISIM simulator to verify its functionality. The core was also synthesized on Xilinx FPGA with device number XC5VLX50T. The resultant operating frequency of the proposed parallel loader was 389.03 MHz. In terms of performance speed up, the proposed loader reduces the configuration time to be higher performance than reported architectures in literature. In terms of area utilization, the proposed parallel loader used slices' LUT to store the substitution matrix scores instead of using the block RAM. This reduces the design dependency on the restricted block RAM elements in FPGA. In terms of slice utilization, the proposed parallel loader utilized 57 slices when implemented in Xilinx Virtex-5 FPGA. With the total slices of 7200, the loader only utilized 0.79% of the FPGA area, thus allows for more generation of bigger PEs systolic array in FPGA.