Design a high gain low noise amplifier for 5G wireless network using 0.18 µm CMOS technology

The transceiver is a combination of receiver and transmitter circuits. The components in the transceiver should be able to suit 5G requirements. A low-noise amplifier (LNA) is the most critical component in a radio frequency (RF) receiver chain of 5G network communication. It amplifies weak incoming signals, typically received from an antenna. Its primary function is to increase the amplitude of the signal while introducing as little noise as possible. A novel design of LNA for 3.5 GHz is proposed by using 0.18 µm complementary metal-oxide semiconductor (CMOS) technology with topology of cascode common source at the input stage and cascade with output common source at output stage. The common source provides a wideband matching at input and output stage circuit network. The cascode topology helps to increase the gain of the LNA. The LNA design was simulated and optimized by using Cadence Virtuoso software. The low supply voltage of 1.8 V and biased voltage, 0.8 V are used to reduce the power consumption. The input return loss, S11 match at -11.36 dB and output return loss, S22 match at -22.65 dB at center frequency 3.5 GHz was achieved on this project. The gain achieved is high gain, represented by S21 at reading of 24.19 dB. The noise figure (NF) is at a moderated value of 4.6 dB. The designed LNA achieves an input third order- intercept point (IIP3) of -9.21 dBm at 3.5 GHz while consuming minimum power of 2.642mW. The overall performance of the LNA, denoted by Figure of Merit (FOM) without considering the linearity or IIP3 as a driven factor, gives a high performance, at the value of 19 (dB (GHz/mW)). With IIP3 as driven factor, the FOM obtained is 1.068