This paper reports on the design, implementation, and characterization of a trench-filled capacitor in complementary Metal-Oxide-Semiconductor (CMOS) grade silicon. In order to achieve high capacitance value in MOS capacitor, trench technology is applied to improved capacitance. The simulation executed by using Synopsys's Sentaurus TCAD. A C-V measurement was done between two different structures of MOS capacitor which are using planar and trench technology. A MOS capacitor with planar technology achieved 4.5 fF meanwhile trench technology achieved a much higher capacitance which is 1.325 pF. A test of varied trench has also been carried out to verify the basic fundamentals of MOS capacitor. It shows that a deeper trench helps to increase higher capacitance.
