One of the great problems in current large-scale integrated circuits is increasing power
dissipation in a small silicon chip. Single-electron transistors which operate by means of oneby-one electron transfer, is relatively small and consume very low power and suitable for
achieving higher levels of integration. In this research, the four masks step are involved
namely source and drain mask, Polysilicon gate mask, contact mask, and metal mask. The
masks were designed using ELPHY Quantum GDS II Editor with a nanowire length and
nanowire width of approximately 0.10µm and 0.010 µm respectively. In addition, the process
flow development of SET and the process and device simulation of SET are also explained in
this paper. The Synopsys TCAD simulation tools are utilized for process and device
simulation. The results from the device simulation showed that the final SET was operating at
room temperature (300K) with a capacitance estimated around 0.4297 aF.
