The purpose of this research is to review and propose a new flow in FPGA Prototyping Flow using a Synopsys Protocompiler tool to solve the stated problem. A fascinating property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as it can borrow time from the shorter paths in the subsequent logic states. Time Borrowing technique is a common approach used to satisfy timing violation in an FPGA prototyped design. However, based on previous studies, more efforts are required to produce an efficient result in closing the timing violation, where lead us to propose a Failed Path Fixes technique. This approach is meant to fix the failed path in a latch due to the gated clock conversion (GCC) process during the synthesis stage which could lead to the timing violation. A solution for prototyping a multi-million logic gates of ASIC/SoC circuit into the FPGA platform for verification purpose is by partition the design into multi-FPGA. This research is focusing on the required partition requirement to successfully prototype the large SoC circuit into the multi-FPGA. The presence of cut clocks in a circuit after partition stage will result in the failure in routing stage due to the congestion error. Therefore, an approach proposed in this research to resolve this challenge is Manual Clock Distribution technique, so that design is able to meet the partition requirement to complete the prototyping process into multi-FPGA. The combination of our Failed Path Fixes and time borrowing technique are able to solve the timing violation problem by eliminating the unnecessary path created by protocompiler tool. Comparison of numbers of negative slack before and after our proposed technique is applied resulting 90% improvement. The manual clock distribution technique proposed has been able to solve the cut clock issue that leads to routing congestion problem when partitioning a circuit into two FPGA chips. With our proposed technique, all partition requirements are met and I 00% cut clock elimination is achieved.
