Home
  • English
  • ÄŒeÅ¡tina
  • Deutsch
  • Español
  • Français
  • Gàidhlig
  • LatvieÅ¡u
  • Magyar
  • Nederlands
  • Português
  • Português do Brasil
  • Suomi
  • Log In
    New user? Click here to register. Have you forgotten your password?
Home
  • Browse Our Collections
  • Publications
  • Researchers
  • Research Data
  • Institutions
  • Statistics
    • English
    • ÄŒeÅ¡tina
    • Deutsch
    • Español
    • Français
    • Gàidhlig
    • LatvieÅ¡u
    • Magyar
    • Nederlands
    • Português
    • Português do Brasil
    • Suomi
    • Log In
      New user? Click here to register. Have you forgotten your password?
  1. Home
  2. Research Output and Publications
  3. Faculty of Electronic Engineering & Technology (FKTEN)
  4. Theses & Dissertations
  5. Design and implementation of parallel model embedded FPGA-based computing architecture for DES algorithm
 
Options

Design and implementation of parallel model embedded FPGA-based computing architecture for DES algorithm

Date Issued
2021
Author(s)
Husham Ibrahim Mahdi Al-Salman
Handle (URI)
https://hdl.handle.net/20.500.14170/2636
Abstract
Over the past few years, there has been exponential growth within the field of cloud computing because the need for services on the go for mobile platforms has seen a speedy increase in demand. This success has spurred the requirement for multiplied security measures for cloud computing. Security is the primary issue for the cloud as well as other internet services. The primary reason preventative of the complete adoption of cloud computing is in truth the various security problems it comes with, despite how useful it is going to be. Two major problems have been confronting these platforms; firstly, delay in data processing, and secondly, security hazards for potential threats. The conclusion from these platforms is unable to fulfill the whole security challenge for fast processing and hazard reduction. These two problems had been solved through a DES algorithmic redesign in three designs namely, single, dual, and multiple (quad) engines to encrypt/decrypt components to be carried out as the fast design. So, for maximizing the throughput, this architecture can provide one block of cipher for each block cycle. Furthermore, in order to perform maximum throughput, the critical path which is the longest path between two registers is reduced to one stage. This was performed by using two 32 bit/s registers at the end of every round in order to hold the partial cipher and reach the highest throughput. This model is duplicated and multiple (quads) by means of the spatial parallelism technique. A comparison between them was made to find the best design, and then the selected design was compared with external studies for finding the best method of it. This analysis has strengthened the hand, the encryption of more than one block was achieved at a time and over the number of designs to find the most suitable application for data processing. This study implemented a DES algorithm-based efficient for the design of 16-round multiple parallel engines for low-cost, scalable, and powerful encryption solution for hardware implementation which has a high frequency of 227 MHz and achieved a throughput of 58,288.64 Mbps.
Subjects
  • DES algorithm

  • Cloud computing

File(s)
Page 1-24.pdf (1.45 MB) Full Text.pdf (21.22 MB) Declaration Form.pdf (678.58 KB)
Views
3
Acquisition Date
Nov 19, 2024
View Details
Downloads
13
Acquisition Date
Nov 19, 2024
View Details
google-scholar
  • About Us
  • Contact Us
  • Policies