Generally, data transfer is a key factor when it comes to communicate between different users of the Internet or any local area networks for the information to be shared or distributed. The major problems when transferring data are bandwidth limitation, data processing delay and design complexity. In this project the design and implementation on embedded Ethernet controller is performed on cyclone IlJ FPGA starter Nios Embedded Evaluation Kit (NEEK) board. Field Programmable Gate Arrays (FPGA) is used to solve mention problems. When it comes to FPGA, data transfer can be implementing much faster than on any other platforms because it offers all of the features required to implement most complex designs. The main objective of this project is to design and implement an embedded Ethernet controller FPGA to achieve true concurrency and lower complexity. Also, verify and evaluate architecture complexity performance in terms of high operating frequency consume as less chip resources and efficient throughput. Spatial parallelism technique has been used to optimize the implementation of embedded Ethernet controller. Furthermore, the operating frequency is enhanced and increased to I GHz by configuring the PLL. The results of embedded Ethernet were shown on the touch screen module of the NEEK
board and on the VGA. The speed of uploading the design images increased because the frequency was enhance to 1 GHz. Spatial approach led to fast data processing and true concurrency with acceptable level of complexity. The structural implementation approach is enabling scalability and portability potentials of proposed design.
