Addition is a fundamental function in the design of a digital system, necessary for applications such as signal processing, arithmetic operations, multiplexers, and control systems. Hence, the digital system’s performance is considerably reliant on the efficiency of the adders. Therefore, designing a 4-bit carry save adder (CSA) that consumes less power, occupies a smaller area, and operates at a higher speed is proposed using the modified–gate diffusion input (MOD–GDI) technique. The primary focus is to reduce the area occupied by decreasing the transistor count as compared with other logic styles (i.e., conventional, and Boolean simplification) for CSA through Cadence Virtuoso simulation based on SilTerra 180 nm technology. Notably, the number of transistors is reduced from 42 in the conventional full adder to 11 in the proposed MOD–GDI design. As a result, the proposed 4-bit CSA with MOD–GDI technique is efficient in improving the speed of addition by reducing the area and power consumption.
