An adder is an important element of all arithmetic and logic units. The recent trend in Nanotechnology is moving towards the need of the devices, which consume low power. The Single Electron Transistor (SET), distinguish by a very small device size low power dissipation, high speed and high performance, is one of the most promising nano electronics devices to replace conventional CMOS. The SET technology offers the ability to control the motion of individual electrons in the designed circuits. In this Full Adder Circuit we were used 24 SET and 14 resistors. The circuit is functioning as required for all the combination of input voltage. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in SET process technology. Also shown is the considerable impact of the supply-voltage scaling on reducing the power expended by leakage and short-circuit. The Low-Power and High-Performance 1-Bit Set Full-Adder digital circuits have been simulated by PSPICE 9.1.
