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  5. Optimization of 14nm horizontal double gate for optimum threshold voltage using L9 Taguchi Method
 
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Optimization of 14nm horizontal double gate for optimum threshold voltage using L9 Taguchi Method

Journal
International Journal of Nanoelectronics and Materials (IJNeaM)
ISSN
1985-5761
Date Issued
2022-12
Author(s)
N.H.N.M. Nizam
Universiti Teknikal Malaysia Melaka
Afifah Maheran A.H
Universiti Teknikal Malaysia Melaka
F. Salehuddin
Universiti Teknikal Malaysia Melaka
K.E. Kaharudin
Lincoln University College
Noor Faizah Z.A.
Limkokwing University of Creative Technology
Handle (URI)
https://ijneam.unimap.edu.my/index.php/vol-15-december-2022-special-issue-bond21
https://ijneam.unimap.edu.my/
https://hdl.handle.net/20.500.14170/3254
Abstract
Silvaco ATHENA TCAD tools are used to model and simulate the electrical properties and characterization of the suggested layout of a 14 nm gate length (Lg) Double Gate Bilayer Graphene Field Effect Transistor (FET). Hafnium Dioxide (HfO2) serves as the high-k material in the negative channel metal oxide semiconductor (NMOS) device, while Tungsten Silicide (WSix) serves as the metal gate. The investigated process parameters are threshold voltage (VTH) adjustment implant dose, threshold voltage (VTH) adjustment tilt angle, source/drain (S/D) implant tilt angle, and source/drain (S/D) implant dose, while the noise factors are threshold voltage (VTH) adjustment implant energy and source-drain (S/D) implant energy. The device was optimized using the Taguchi approach, which incorporates L9 orthogonal arrays and analysis of variance (ANOVA). The most important elements impacting the VTH are the S/D implantation dose. The value of the VTH when compared to the original findings before the optimization is 0.204V, which is 7.059% lower than the desired value. The findings of the optimization procedure show excellent efficiency of the device with a VTH of 0.191, which is 0.007% closer to the 2013 target set by the International Technology Roadmap Semiconductor (ITRS).
Subjects
  • Bi-GFET

  • MOSFET

  • Taguchi

  • Threshold voltage (VT...

File(s)
Optimization of 14nm Horizontal Double Gate for Optimum Threshold Voltage Using L9 Taguchi Method.pdf (1006.18 KB)
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4
Acquisition Date
Mar 5, 2026
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Acquisition Date
Mar 5, 2026
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