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  5. Selective harmonic elimination pulse width modulation for three-phase cascaded multilevel inverter
 
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Selective harmonic elimination pulse width modulation for three-phase cascaded multilevel inverter

Journal
AIP Conference Proceedings
ISSN
0094243X
Date Issued
2021-05-03
Author(s)
Ismail B.
Isa M.
Aikhsan M.Z.
Rohani M.N.K.H.
Wooi C.L.
Rosmi A.S.
DOI
10.1063/5.0044230
Handle (URI)
https://hdl.handle.net/20.500.14170/8911
Abstract
This paper presents an experimental verification of selective harmonic elimination for three-phase cascaded multilevel inverters. The Particle Swarm Optimization (PSO) algorithm is used to compute the non-linear equation for the various modulation indexes of a seven-level three-phase inverter. In addition, the appropriate switching angles are effectively calculated by using the PSO algorithm. Non-triplen harmonics up to 7th order are eliminated. To verify the computational results, the three-phase cascaded multilevel Field Programmable Gate Array (FPGA) based is developed. The results show that the developed multilevel inverter with selective harmonic elimination pulse width modulation switching angles manage to eliminate the lower order harmonics, which is not only for nominal frequency (50 Hz) but also for different operating frequency.
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