Modern computational devices are in the thirst for speedy computation. Adders and multipliers are the major computational units. Various types of multiplier architectures are suggested so far towards faster computation of the product. The speed of the multipliers could be improved by reducing the number of steps required for obtaining the product. One of the methods to reduce the number of steps is Vedic mathematics. There are 16 sutras in ancient Vedic mathematics. This research aims to design a square and cube computation using the Vedic algorithms. Yavadunam sutra (whatever the extent of its deficiency) is used for squaring and Anurupyena sutra (proportionately) is used to compute the cube of the binary number. In the Yavadunam sutra, bit reduction technique is employed to obtain deficiency, thereby, reducing the bit size to N-1 bits. Thus, reduces the delay. Urdhva Tiryagbhyam sutra (vertical and crosswise) is an efficient algorithm used for the multiplication operation. The design was implemented on a Xilinx-Spartan6 (XC6SLX16) FPGA.
