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  4. International Journal of Nanoelectronics and Materials (IJNeaM)
  5. Design and simulation of gate and channel engineered dopingless tunnel FET
 
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Design and simulation of gate and channel engineered dopingless tunnel FET

Journal
International Journal of Nanoelectronics and Materials (IJNeaM)
ISSN
1985-5761
Date Issued
2025-01
Author(s)
Ali Saeed Alzahrani
King Faisal University, Al-Ahsa
DOI
10.58915/ijneam.v18i1.1726
Handle (URI)
https://ejournal.unimap.edu.my/index.php/ijneam/article/view/1726/1077
https://hdl.handle.net/20.500.14170/13711
Abstract
This work presents an innovative device design of a dopingless tunnel field effect transistor (DL-TFET). The device presented in this work is a double gate that uses dual oxide, a dual gate material, and a silicon germanium (SiGe) channel to boost the performance of the proposed device. As such, the device is named a gate and channel engineered dopingless tunnel field effect transistor (GCE-DL-TFET). The use of a high-k material and a suitable work function at the gate and the SiGe channel has considerably enhanced the performance of the GCE-DL-TFET. A fair investigation of the GCE-DL-TFET device with the DL-TFET device reveals significant improvements in ON-current (ION), ION/IOFF ratio, subthreshold slope (SS), and cut-off frequency (fT). The proposed device shows the following increases: ~200 times in ION, 2.5 times in ION/IOFF, and 20 times in fT, as well as 70% improvement in SS. The transient analysis indicates the following decreases: 84% in transient-ON delay and 62% in transient-OFF delay in the GCE-DL-TFET-constructed inverting amplifier in contrast to the DL-TFET-based inverting amplifier.
Subjects
  • Virtual doping

  • Gate and channel engi...

  • Tunneling

  • Dopingless

  • TFET

  • Subthreshold swing

  • Switching performance...

  • MOSFET

  • SiGe.

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Design and simulation of gate and channel engineered dopingless tunnel FET.pdf (688.93 KB)
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