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  3. Faculty of Electronic Engineering & Technology (FKTEN)
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  5. Enhanced implementation of embedded concurrent processors using NIOSII and shared memory on FPGA for better workload balance
 
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Enhanced implementation of embedded concurrent processors using NIOSII and shared memory on FPGA for better workload balance

Date Issued
2016
Author(s)
Mays Qahtan Sedeeq
School of Computer and Communication Engineering
Handle (URI)
https://hdl.handle.net/20.500.14170/14978
Abstract
The existence of modem demanding applications and their need for high computational power motivate designers to look for an adaptive system that would handle the uprising challenges. MPSoC merges as a very promising solution that would provide real time performance and also addresses other critical parameters such as cost, power consumption and the utilisation of on chip area. The design of a multiprocessor that shares memory suffers from some issues. Synchronising the access of the connected processors to the shared memory is the first problem faced along with the possibility of having thread safety that may cause computing faults. The possibility of having deadlocks is the second problem and it was addressed by designing a hierarchical system with high efficiency in handling interrupts. As the connected processors start running a given application, the issue of having either an idle processor or overloaded one could decrease the overall performance, thus applying the load balancing algorithm is a significant step to achieve the demanded enhancement. Field Programmable Gate Array (FPGA) was found very efficient in constructing and enhancing the implementation of embedded concurrent processor. The selected board in the proposed design was Niosii Embedded Evaluation Kit (NEEK) Cycloneiii edition where the result was to be displayed on the attached LCD multimedia board and on VGA port as welL The design went through two phases, first phase is enhancing the implementation of embedded concurrent processor utilising Niosll and shared memory. Second is validating the design through implementing the Mandelbrot-set as an application and applying the load balancing algorithm. The proposed design is constructed via three Niosll processors connected through the Qsys in a hierarchal master slave style all on one chip. Fast buffers and separate code margins were used to complete the enhancements on the performance of the proposed design. The obtained result showed an increase in the number of displayed frames in one second making speed enhancement up to 20 times the speed of unbalanced multiprocessor. The expanding of this type of system to gain more computing power must be considered to satisfy the uprising demanding applications in the future.
Subjects
  • Embedded computer sys...

  • Field programmable ga...

  • Multiprocessors

  • Parallel computing

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