A new verification technique with real time simulation and post processing simulation is proposed. It aims to reduce the time for verification, simulation time as well as time for debugging. This approach will give more advantage if simulate for a large scale design since no checking process is involved during real time simulation and hence will consumes less time to simulate. Resimulation on the design itself to reproduce waveform for validation which will consume more time can be avoided. During real time simulation, UVM testbench is mainly used to obtain the inputs driven into DUT and output received from DUT by introducing eight different inputs of plaintext and globalkey into sequence. After real time simulation is completed, post processing simulation is started with the tracker extracts the inputs from input monitor and outputs from output monitor. The inputs extracted from input monitor are sent into lookup table to search for reference output. A comparison between reference output from lookup table and output extracted from output monitor is performed. The simulation results are analyzed to evaluate whether the aims can be achieved or not.
