Sohiful Anuar Zainol Murad
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Preferred name
Sohiful Anuar Zainol Murad
Official Name
Sohiful Anuar, Zainol Murad
Alternative Name
Murad, S. A.Zainol
Murad, S. A.Zainol
Anuar, Zainol Murad Sohiful
Zainol Murad, S.A.
Sohiful, Z. M.A.
Main Affiliation
Scopus Author ID
16643180100
Researcher ID
I-1082-2019

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  • Publication
    Design and characterization of a 3.5 GHz CMOS power amplifier for low-band 5G applications
    (Taylor and Francis Ltd., 2025)
    Ahmad Fariz Hasan
    ;
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    ;
    Rohana Sapawi
    A 3.5 GHz CMOS power amplifier (PA) designed for 5G applications is presented in this study, utilizing the 0.18 µm RF CMOS process technology. The circuit architecture comprises two stages: the first stage employs a cascode topology with a negative voltage applied to the transistor body technique to achieve sufficient gain and minimize current, thereby reducing power consumption. In the second stage, to ensure high efficiency, a class-E amplifier is being used. Measurement results indicate a power gain (S21) of 17.2 dB, a power-added efficiency (PAE) of 45.6% and a saturated power (Psat) of 8.5 dBm, obtained at 3.5 GHz. These findings validate the suitability of the proposed design at low-band frequency for 5G applications. The chip area for the proposed design is 2.45 mm². The discrepancy between simulation and measurement is due to the parasitic in the layout design.
  • Publication
    Review of efficiency CMOS class AB power amplifier topology in gigahertz frequencies
    ( 2022-01-01)
    Sapawi R.
    ;
    Ahmad D.A.S.
    ;
    Ping K.H.
    ;
    Julai N.
    ;
    Kipli K.
    ;
    Sawawi M.
    ;
    Masra S.M.W.
    ;
    Sohiful Anuar Zainol Murad
    This paper reviewed the efficiency of CMOS class AB power amplifier topology especially in gigahertz frequencies. CMOS class AB power amplifier is a compromise between class A and class B in terms of linearity and efficiency between 50% to 78.5%. However, CMOS class AB power amplifier cannot have good linearity and efficiency simultaneously due to the breakdown in gate-oxide voltage and effects from hot carrier. The breakdown of oxide prevents optimum drain signal and the effect from hot carrier will reduce the quality of the overall PA design. Several works from year 1999 to 2019 with different topology such as multiple gated transistor, cascode, feedforward linearization, differential circuit, transformer combining method with common source harmonic termination and combination of a dual-switching transistor with a third harmonic tuning technique are discussed and the performances of the power amplifier are compared. The best three CMOS class AB power amplifier topologies were chosen in terms of high efficiency. The topologies are two stages with integrated input and interstage matching, Doherty amplifier combined with drain modulation based architectures and self-biased cascode topology that obtained power added efficiency of 45%, 43% and 42%, respectively. Key performance indicators for class AB power amplifier include frequency, power added efficiency, gain and output power are also discussed in this paper.
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