Sohiful Anuar Zainol Murad
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Preferred name
Sohiful Anuar Zainol Murad
Official Name
Sohiful Anuar, Zainol Murad
Alternative Name
Murad, S. A.Zainol
Murad, S. A.Zainol
Anuar, Zainol Murad Sohiful
Zainol Murad, S.A.
Sohiful, Z. M.A.
Main Affiliation
Scopus Author ID
16643180100
Researcher ID
I-1082-2019

Research Output
Now showing 1 - 2 of 2
  • Publication
    UWB CMOS low noise amplifier for mode 1
    ( 2017-07-02)
    Tun Zainal Azni Zulkifli
    ;
    Arjuna Marzuki
    ;
    Sohiful Anuar Zainol Murad
    This paper presents an ultra-wideband 3.1-4.9 GHz low noise amplifier (LNA) employing a sixth-order bandpass Chebyshev filter. The LNA has been designed using Silterra 0.18 μm CMOS technology at 1.8 V power supply. The simulation shows that the LNA attains a power gain of 14.1 dB with an input reflection coefficient less than -10 dB in frequency range of interest, a noise figure of 4.29 dB at 3.8 GHz, gain flatness of ±0.25 dB, a 1 dB compression point of -17.67 dBm, -6.90 dBm for IIP3 and power dissipation of 4.5 mW excluding the buffer stage.
  • Publication
    Design of a 24.5 GHZ CMOS low noise amplifier using 0.13-µM technology for 6G wireless applications
    (Penerbit UTM Press, 2025-11-11)
    Sohiful Anuar Zainol Murad
    ;
    Asrulnizam Abd Manaf
    ;
    Nuha A. Rhaffor
    ;
    Ruhaifi Abdullah Zawawi
    The need for high-performance circuit designs is growing as wireless communication technologies continue to advance and support newer generations of wireless applications. Much emphasis has been focused on the possibility of the 24 GHz frequency band in next-generation wireless networks, including 5G and beyond. Designing a low noise amplifier (LNA) operating at 24 GHz presents several challenges. The primary concerns include achieving high gain, low power consumption, low noise figure, and while maintaining good linearity and stability. This paper presents the design, simulation, and layout of a CMOS LNA optimized for operation at 24.5 GHz frequency, targeting 6G and beyond wireless communication applications. The proposed LNA employs three stages with a cascode topology at the first stage and follow by a common source stage at second and third stage. The three stages help to achieve high gain, and the source degeneration inductor at the first stage helps to improve linearity. Extensive simulations were conducted using a 0.13-µm CMOS technology, demonstrating a peak gain of 21 dB and a noise figure of 5.6 dB at 24.5 GHz. The LNA also exhibits good linearity and stability over a wide bandwidth. The performance metrics were validated through simulation and comparison, showcasing the feasibility of the designed LNA for 6G applications. This work contributes to the advancement of CMOS-based radio frequency (RF) front-end designs for next-generation wireless communication systems.