Sohiful Anuar Zainol Murad
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Preferred name
Sohiful Anuar Zainol Murad
Official Name
Sohiful Anuar, Zainol Murad
Alternative Name
Murad, S. A.Zainol
Murad, S. A.Zainol
Anuar, Zainol Murad Sohiful
Zainol Murad, S.A.
Sohiful, Z. M.A.
Main Affiliation
Scopus Author ID
16643180100
Researcher ID
I-1082-2019

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  • Publication
    A 0.89 to 2.1 GHz Tunable Power Amplifier for Multi-band Transmitter
    ( 2023-01-01)
    Sapawi R.
    ;
    Kipli K.
    ;
    Julai N.
    ;
    Hong Ping K.
    ;
    Sohiful Anuar Zainol Murad
    ;
    Awg Salleh D.N.S.
    This paper presents a multi-band power amplifier by using Benzocyclobutene inductor and tunable barium strontium titanate capacitor to achieve high quality (Q) factor to improve narrow bandwidth in tunable of power amplifier. The proposed power amplifier employed two stages with resistive shunt feedback at the input stage to provide a broadband gain and steady wideband input matching. Tunable frequency range from 0.89 GHz to 2.1 GHz is conducted by tunable BST capacitor from 1 pF to 20 pF. The tunable power amplifier achieves high power gain, good input and output matching, low power consumption and good power added efficiency over all frequency range of interest. It can be concluded that the proposed multi-band power amplifier is quite promising for future mobile terminals application.
  • Publication
    Design of High-Quality Factor Active Indictor Using CMOS 0.18-μm Technology for 5G Applications
    ( 2022-01-01)
    Ali H.A.A.A.
    ;
    Sohiful Anuar Zainol Murad
    ;
    Hasan A.F.
    ;
    Faizah Abu Bakar
    ;
    Sapawi R.
    This paper presents high quality factor of active inductor circuit for 5G application. The proposed circuit is based on the differential active inductor (DAI) topology. The DAI is designed using CMOS 0.18 μm technology. The quality factor (Q) can be tuned with the current source values, ranging from 0.5 mA to 3 mA, while the voltage can control the inductance values L. Meanwhile, the frequency range can be controlled with the feedback resistance. The simulation results indicate that the Q factor as large as 262.5k can be achieved with inductor values of 10 nH at frequency 3.2 GHz. In addition, the Q factor of 1650 is obtained at 3.5 GHz. The performance comparison with previously published works is also demonstrated and found that the proposed DAI is suitable for 5G application.
  • Publication
    The analysis of low phase nonlinearity 3.1-6 GHz CMOS power amplifier for UWB system
    ( 2017-01-01)
    Sapawi R.
    ;
    Salleh D.
    ;
    Sahari S.
    ;
    Masra S.
    ;
    Mat D.
    ;
    Kipli K.
    ;
    Sohiful Anuar Zainol Murad
    Low phase nonlinearity is important criteria in power amplifier (PA) especially in ultra-wideband system so that the output will remain original identity. Up to date there is no analysis study have been established in achieving low group delay PA in UWB technology, therefore this paper is to examined the factors that affect low phase nonlinearity in 3.1-6.0 GHz PA using two-stage amplifier with shunt resistive feedback technique for UWB system. The proposed PA adopts two stages amplifier together with inter-stage circuit to obtain adequate flatness of the gain. The shunt resistive feedback topology is used to have very wide input matching. The inductive peaking technique and Class A amplifier is adopted to obtain high gain flatness, low phase nonlinearity and linearity simultaneously. The analysis shows that the dominant factor is identified for low phase nonlinearity in UWB PA. The proposed PA achieves the average gain of 10±1 dB, S11<-6dB, S22< -7 dB, and phase nonlinearity of ±195.5 ps. A good linearity and power consumption are obtained. Therefore, these key performance factors of low phase nonlinearity can be applied to facilitate other researchers working in the area of power amplifier circuit design.
  • Publication
    Design of low power Wallace tree multiplier using modified full adder
    ( 2024-02-08)
    Ahmad Fariz Hasan
    ;
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    ;
    Husin M.F.C.
    ;
    Sapawi R.
    High speed and energy-efficient of a device are essential in the electronics industry due to the high demand for multimedia usage and fast technology. Multipliers play a vital role, especially in the processor's integrated circuits, microprocessors, filters, and arithmetic units. Wallace tree multiplier works in parallel, making it an efficient multiplier in terms of area and speed. Internally, a multiplier consists of Adder, which is full Adder (FA) and half Adder (HA). Full adders give a significant contribution to making a multiplier that works very well. A processor or chip performs very efficiently and effectively when running at high speed, in a small area, and at low power. Modification of full Adder in Wallace tree multiplier helps to consume low power during multiplication. In this project, 4-bit and 8-bit Wallace tree multipliers are designed. The design is developed in Verilog HDL and simulated the functionalities using Quartus II software. Mentor Graphic software was used to produce the final layout of 8 x 8-bit Wallace tree multiplier. The modified Wallace tree multiplier shows 64.97mW power lower than the conventional multiplier, which was 65.88mW.
  • Publication
    CMOS power amplifier design techniques for UWB communication: A review
    ( 2017-01-01)
    Sapawi R.
    ;
    Mohamad D.
    ;
    Yusuf D.
    ;
    Sahari S.
    ;
    Salleh D.
    ;
    Hazis N.
    ;
    Sohiful Anuar Zainol Murad
    This paper reviews CMOS power amplifier (PA) design techniques in favour of ultra-wideband (UWB) application. The PA circuit design is amongst the most difficult delegation in developing the UWB transmitter due to conditions that must be achieved, including high gain, good input and output matching, efficiency, linearity, low group delay and low power consumption. In order to meet these requirements, many researchers came up with different techniques. Among the techniques used are distributed amplifiers, resistive shunt feedback, RLC matching, shunt-shunt feedback, inductive source degeneration, current reuse, shunt peaking, and stagger tuning. Therefore, problems and limitation of UWB CMOS PA and circuit topology are reviewed. A number of works on the UWB CMOS PA from the year 2004 to 2016 are reviewed in this paper. In recent developments, UWB CMOS PA are analysed, hence imparting a comparison of performance criteria based on several different topologies.
  • Publication
    Ultra-Low Power 0.55 mW 2.4 GHz CMOS Low-Noise Amplifier for Wireless Sensor Network
    ( 2022-01-01)
    Sohiful Anuar Zainol Murad
    ;
    Azizan A.
    ;
    Sapawi R.
    ;
    Zulkifli T.Z.A.
    This paper describes the design topology of two-stage ultra-low power low noise amplifier (LNA) using the forward body bias technique for wireless sensor network (WSN) application. The proposed design employs CMOS 0.13-µm technology at 2.4 GHz frequency. The LNA consumes low power from the forward body bias technique at the first and the second stages. The threshold voltage of the transistor can be lowered using the forward body bias technique. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The measurement results show that the LNA consumes a total power of 0.55 mW at supply voltage 0.55 V. The input return loss (S11) and the output return loss (S22) is 10 and 12 dB, respectively. A gain of 12 dB, noise figure (NF) of 5.9 dB and input third-order intercept point (IIP3) of −3 dBm are achieved.
  • Publication
    Review of efficiency CMOS class AB power amplifier topology in gigahertz frequencies
    ( 2022-01-01)
    Sapawi R.
    ;
    Ahmad D.A.S.
    ;
    Ping K.H.
    ;
    Julai N.
    ;
    Kipli K.
    ;
    Sawawi M.
    ;
    Masra S.M.W.
    ;
    Sohiful Anuar Zainol Murad
    This paper reviewed the efficiency of CMOS class AB power amplifier topology especially in gigahertz frequencies. CMOS class AB power amplifier is a compromise between class A and class B in terms of linearity and efficiency between 50% to 78.5%. However, CMOS class AB power amplifier cannot have good linearity and efficiency simultaneously due to the breakdown in gate-oxide voltage and effects from hot carrier. The breakdown of oxide prevents optimum drain signal and the effect from hot carrier will reduce the quality of the overall PA design. Several works from year 1999 to 2019 with different topology such as multiple gated transistor, cascode, feedforward linearization, differential circuit, transformer combining method with common source harmonic termination and combination of a dual-switching transistor with a third harmonic tuning technique are discussed and the performances of the power amplifier are compared. The best three CMOS class AB power amplifier topologies were chosen in terms of high efficiency. The topologies are two stages with integrated input and interstage matching, Doherty amplifier combined with drain modulation based architectures and self-biased cascode topology that obtained power added efficiency of 45%, 43% and 42%, respectively. Key performance indicators for class AB power amplifier include frequency, power added efficiency, gain and output power are also discussed in this paper.
      1
  • Publication
    Ultra-Low Power 0.55 mW 2.4 GHz CMOS Low-Noise Amplifier for Wireless Sensor Network
    ( 2022-01-01)
    Sohiful Anuar Zainol Murad
    ;
    Anishaziela Azizan
    ;
    Sapawi R.
    ;
    Zulkifli T.Z.A.
    This paper describes the design topology of two-stage ultra-low power low noise amplifier (LNA) using the forward body bias technique for wireless sensor network (WSN) application. The proposed design employs CMOS 0.13-µm technology at 2.4 GHz frequency. The LNA consumes low power from the forward body bias technique at the first and the second stages. The threshold voltage of the transistor can be lowered using the forward body bias technique. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The measurement results show that the LNA consumes a total power of 0.55 mW at supply voltage 0.55 V. The input return loss (S11) and the output return loss (S22) is 10 and 12 dB, respectively. A gain of 12 dB, noise figure (NF) of 5.9 dB and input third-order intercept point (IIP3) of −3 dBm are achieved.
      1
  • Publication
    Design of High-Quality Factor Active Indictor Using CMOS 0.18-μm Technology for 5G Applications
    ( 2022-01-01)
    Ali H.A.A.A.
    ;
    Sohiful Anuar Zainol Murad
    ;
    Ahmad Fariz Hasan
    ;
    Faizah Abu Bakar
    ;
    Sapawi R.
    This paper presents high quality factor of active inductor circuit for 5G application. The proposed circuit is based on the differential active inductor (DAI) topology. The DAI is designed using CMOS 0.18 μm technology. The quality factor (Q) can be tuned with the current source values, ranging from 0.5 mA to 3 mA, while the voltage can control the inductance values L. Meanwhile, the frequency range can be controlled with the feedback resistance. The simulation results indicate that the Q factor as large as 262.5k can be achieved with inductor values of 10 nH at frequency 3.2 GHz. In addition, the Q factor of 1650 is obtained at 3.5 GHz. The performance comparison with previously published works is also demonstrated and found that the proposed DAI is suitable for 5G application.
      3
  • Publication
    Design of CMOS low-dropout voltage regulator for power management integrated circuit in 0.18-μm technology
    ( 2020-01-08)
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Mohd Nazrin Md Isa
    ;
    Shaiful Nizam Mohyar
    ;
    Sapawi R.
    ;
    Karim J.
    A low-dropout (LDO) voltage regulator is the main component used in the majority of portable electronic application since it is used as power management unit in those applications. In this paper, a LDO regulator for the power management integrated circuit in 0.18-μm CMOS technology using Cadence software is presented. The error amplifier of the proposed LDO employed seven transistors for current mirror. Meanwhile, the PMOS transistor is used as a pass element transistor to control the voltage variation. The resistors are used as a feedback network circuit while the capacitor is used to minimise the variation of output voltage. The simulation results show that the proposed design provides a 2.41 V constant output voltage for the supply voltage ranges of 2.55 V to 3.55 V. The dropout voltage of 140 mV is achieved with 1.48 mW power consumption. The line regulation is 1.0 mV/V and the load regulation is 0.41 mV/A, while the layout of the proposed regulator is 27 μm × 34 μm.
      1