Amiza Amir
Thumbnail Image
Preferred name
Amiza Amir
Official Name
Amiza, Amir
Main Affiliation
Scopus Author ID
36170326400
Researcher ID
EKV-8568-2022

Research Output

Filters

6
6
Reset filters

Settings
Now showing 1 - 6 of 6
  • Publication
    A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform
    ( 2023-01-01)
    Mohammed N.Q.
    ;
    Amiza Amir
    ;
    R Badlishah Ahmad
    ;
    Salih M.H.
    ;
    Arrfou H.
    ;
    Thalji N.
    ;
    Matem R.
    ;
    Abbas J.K.K.
    ;
    Hussien Q.M.
    ;
    Abdulhassan M.M.
    High-security cryptography algorithms like AES require high computational capabilities to achieve information security. Therefore, it is necessary to use parallel computing architectures that exploit modern technologies to obtain the most conceivable computational power. Various methods have been introduced to achieve parallel processing. One of them is field-programmable gate arrays (FPGAs), which have good characteristics suitable for implementing parallel architectures with lower power consumption. This paper will focus on the most important FPGA boards that were used to implement the AES cryptographic algorithm. In addition, it demonstrates the general scheme of building architecture with multiple computing processing engines to get high performance and better throughput, which is reflected in the reduced cost and energy consumption of IoT devices.
  • Publication
    On the effectiveness of congestion control mechanisms for remote healthcare monitoring system in IoT environment - A review
    ( 2017-01-03)
    Wan Aida Nadia Wan Abdullah
    ;
    Naimah Yaakob
    ;
    R Badlishah Ahmad
    ;
    Amiza Amir
    ;
    Siti Asilah Yah
    A progressive advancement in biosensors and wireless technology are the major contributors to the realization of continuous remote health monitoring system (RHMS). Wireless Body Area Network (WBAN) is part of this technology due to the deployment of multiple sensors such as Electrocardiogram (ECG) to collect vital body signals for processing and diagnosis. Among the benefits offered by this technology include remote monitoring of patient's health status and early detection of abnormalities in the collected signals. Once detected, several preventive measurements can be taken. However, this system needs to encounter some challenges in the wireless network such as delay, packet loss and throughput due to network congestion when transmitting and receiving a bulk of multiple data. Generally, the presence of these problems in transmitting vital body signals may result in incorrect medical diagnosing which can increase mortality rate and cause severe impact to the overall system's performance. Thus, a suitable design of congestion control mechanism is urgently needed in designing a reliable and efficient remote health monitoring system.
  • Publication
    Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA
    ( 2022-01-01)
    Mohammed N.Q.
    ;
    Amiza Amir
    ;
    Salih M.H.
    ;
    R Badlishah Ahmad
    Applications, such as Internet of Things, deal with huge amount of transmitted, processed and stored images that required a high computing capability. Therefore, there is a need a computing architecture that contribute in increasing the throughput by exploiting modern technologies in both spatial and temporal parallelisms. This paper conducts a parallel quad-engine cybersecurity architecture with new configuration to increase the throughput. using DE1-SoC and Neek FPGA boards and HDL. In this architecture, each engine operates with 600MHz maximum frequency. Each image is divided into four parts of equal size and each part processed by single engine concurrently to achieve spatial parallelism. Internally, engine is handling image’s part in temporal parallelism and deep pipelining abstraction applied in every engine by dividing it to sub modules to execute different tasks concurrently. All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture. The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of processing
  • Publication
    Performance Analysis of Congestion Control Mechanism in Software Defined Network (SDN)
    ( 2017-12-11)
    Rahman M.Z.A.
    ;
    Naimah Yaakob
    ;
    Amiza Amir
    ;
    R Badlishah Ahmad
    ;
    Yoon See Ki
    ;
    Abd Halim A.H.
    In the near future, the traditional networks architecture will be difficult to be managed. Hence, Software Defined Network (SDN) will be an alternative in the future of programmable networks to replace the conventional network architecture. The main idea of SDN architecture is to separate the forwarding plane and control plane of network system, where network operators can program packet forwarding behaviour to improve the network performance. Congestion control is important mechanism for network traffic to improve network capability and achieve high end Quality of Service (QoS). In this paper, extensive simulation is conducted to analyse the performance of SDN by implementing Link Layer Discovery Protocol (LLDP) under congested network. The simulation was conducted on Mininet by creating four different fanout and the result was analysed based on differences of matrix performance. As a result, the packet loss and throughput reduction were observed when number of fanout in the topology was increased. By using LLDP protocol, huge reduction in packet loss rate has been achieved while maximizing percentage packet delivery ratio.
  • Publication
    Implementation Dual Parallelism Cybersecurity Architecture on FPGA
    ( 2022-05-01)
    Mohammed N.Q.
    ;
    Amiza Amir
    ;
    Salih M.H.
    ;
    Arrfou H.
    ;
    Hussein Q.M.
    ;
    R Badlishah Ahmad
    This paper presents an efficient parallelism architecture that uses a dual-computing engine architecture to better throughput using both spatial and temporal parallelism on FPGA technology. This architecture will enhance the performance in terms of operating frequency and throughput and reduces the power consumption that meets applications with huge data processing such as Internet of Things in this design, two boards are used, "DE1_Soc and NEEK board" with Altera Quartus Prime 18 for synthesis and simulation. The proposed design architecture gives better resource usage and throughput through fewer hardware redundancies using a frequency of 600MHZ with 64 bits for each engine from the dual-engine. Furthermore, the proposed architecture implementation results show the reduction in the time delay by 40 % and achieves a throughput of 153.6 Gb/s.
  • Publication
    Image classification for snake species using machine learning techniques
    ( 2017-01-01)
    Amiza Amir
    ;
    Nik Adilah Hanin Zahri
    ;
    Naimah Yaakob
    ;
    R Badlishah Ahmad
    This paper investigates the accuracy of five state-of-the-art machine learning techniques — decision tree J48, nearest neighbors, knearest neighbors (k-NN), backpropagation neural network, and naive Bayes — for image-based snake species identification problem. Conventionally, snake species identification is conducted manually based on the observation of the characteristics such head shape, body pattern, body color, and eyes shape. Images of 22 species of snakes that can be found in Malaysia were collected into a database, namely the Snakes of Perlis Corpus. Then, an intelligent approach is proposed to automatically identify a snake species based on an image which is useful for content retrieval purpose where a snake species can be predicted whenever a snake image is given as input. Our experiment shows that backpropagation neural network and nearest neighbour are highly accurate with greater than 87% accuracy on CEDD descriptor in this problem.