Amiza Amir
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Preferred name
Amiza Amir
Official Name
Amiza, Amir
Main Affiliation
Scopus Author ID
36170326400
Researcher ID
EKV-8568-2022

Research Output
Now showing 1 - 3 of 3
  • Publication
    A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform
    ( 2023-01-01)
    Mohammed N.Q.
    ;
    Amiza Amir
    ;
    R Badlishah Ahmad
    ;
    Salih M.H.
    ;
    Arrfou H.
    ;
    Thalji N.
    ;
    Matem R.
    ;
    Abbas J.K.K.
    ;
    Hussien Q.M.
    ;
    Abdulhassan M.M.
    High-security cryptography algorithms like AES require high computational capabilities to achieve information security. Therefore, it is necessary to use parallel computing architectures that exploit modern technologies to obtain the most conceivable computational power. Various methods have been introduced to achieve parallel processing. One of them is field-programmable gate arrays (FPGAs), which have good characteristics suitable for implementing parallel architectures with lower power consumption. This paper will focus on the most important FPGA boards that were used to implement the AES cryptographic algorithm. In addition, it demonstrates the general scheme of building architecture with multiple computing processing engines to get high performance and better throughput, which is reflected in the reduced cost and energy consumption of IoT devices.
  • Publication
    Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA
    ( 2022-01-01)
    Mohammed N.Q.
    ;
    Amiza Amir
    ;
    Salih M.H.
    ;
    R Badlishah Ahmad
    Applications, such as Internet of Things, deal with huge amount of transmitted, processed and stored images that required a high computing capability. Therefore, there is a need a computing architecture that contribute in increasing the throughput by exploiting modern technologies in both spatial and temporal parallelisms. This paper conducts a parallel quad-engine cybersecurity architecture with new configuration to increase the throughput. using DE1-SoC and Neek FPGA boards and HDL. In this architecture, each engine operates with 600MHz maximum frequency. Each image is divided into four parts of equal size and each part processed by single engine concurrently to achieve spatial parallelism. Internally, engine is handling image’s part in temporal parallelism and deep pipelining abstraction applied in every engine by dividing it to sub modules to execute different tasks concurrently. All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture. The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of processing
  • Publication
    Implementation Dual Parallelism Cybersecurity Architecture on FPGA
    ( 2022-05-01)
    Mohammed N.Q.
    ;
    Amiza Amir
    ;
    Salih M.H.
    ;
    Arrfou H.
    ;
    Hussein Q.M.
    ;
    R Badlishah Ahmad
    This paper presents an efficient parallelism architecture that uses a dual-computing engine architecture to better throughput using both spatial and temporal parallelism on FPGA technology. This architecture will enhance the performance in terms of operating frequency and throughput and reduces the power consumption that meets applications with huge data processing such as Internet of Things in this design, two boards are used, "DE1_Soc and NEEK board" with Altera Quartus Prime 18 for synthesis and simulation. The proposed design architecture gives better resource usage and throughput through fewer hardware redundancies using a frequency of 600MHZ with 64 bits for each engine from the dual-engine. Furthermore, the proposed architecture implementation results show the reduction in the time delay by 40 % and achieves a throughput of 153.6 Gb/s.