Ahmad Fariz Hasan
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Preferred name
Ahmad Fariz Hasan
Official Name
Hasan, Ahmad Fariz
Alternative Name
Hasan, A. F.
Hassan, Fariz
Hasan, Ahmad Fariz
Hassan, Ahmad Fariz
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Scopus Author ID
55975778800
Researcher ID
DWG-8508-2022

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Design and characterization of a 3.5 GHz CMOS power amplifier for low-band 5G applications

2025 , Ahmad Fariz Hasan , Sohiful Anuar Zainol Murad , Faizah Abu Bakar , Rohana Sapawi

A 3.5 GHz CMOS power amplifier (PA) designed for 5G applications is presented in this study, utilizing the 0.18 µm RF CMOS process technology. The circuit architecture comprises two stages: the first stage employs a cascode topology with a negative voltage applied to the transistor body technique to achieve sufficient gain and minimize current, thereby reducing power consumption. In the second stage, to ensure high efficiency, a class-E amplifier is being used. Measurement results indicate a power gain (S21) of 17.2 dB, a power-added efficiency (PAE) of 45.6% and a saturated power (Psat) of 8.5 dBm, obtained at 3.5 GHz. These findings validate the suitability of the proposed design at low-band frequency for 5G applications. The chip area for the proposed design is 2.45 mm². The discrepancy between simulation and measurement is due to the parasitic in the layout design.

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Publication

Power Amplifier for 5G Technology

2023 , Ahmad Fariz Hasan , Sohiful Anuar Zainol Murad

This book has significant value to all level of students both undergraduates as well as, postgraduate students, researchers, and engineers in the field of radio-frequency integrated circuit (RFIC) design. This book provides comprehensive understanding state-of-the-art for RF design specifically radio frequency (RF) power amplifier design. It covers overview of 5G technology, fundamental of power amplifier, design implementation of 5G power amplifier, schematic design, layout and simulation results with an in-depth illustrative discussions and up-to-date references. It is useful as a reference and essential book for high-frequency circuit designers in both academia and industry.

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High linearity multi-band CMOS low noise amplifier at 2.4/3.5 GHz for 4G/5G applications

2024-02-08 , Sohiful Anuar Zainol Murad , Azizan A. , Faizah Abu Bakar , Ahmad Fariz Hasan , Marzuki A. , Zulkifli T.Z.A.

This paper presents a high linearity multi-band CMOS low noise amplifier (LNA) at 2.4/3.5 GHz for wireless application. The proposed multi-band CMOS LNA is targeted for concurrent 2.4 GHz and 3.5 GHz bands for 4G and 5G wireless technology, respectively. A cascoded topology with bandpass and bandstop filter at the input is utilized to achieve multiple-band frequency at 2.4 GHz and 3.5 GHz. The LNA is implemented and simulated using CMOS 0.13 μm process in Cadence Virtuoso Analog Design Environment software. The simulation results indicate that the gain (S21) of 15 dB/11 dB with the third order intercept point (IIP3) of 2.04 dBm/3.80 dBm at 2.4 GHz/3.5 GHz frequencies are achieved. Meanwhile, the noise figure of 3.0 dB/3.6 dB is obtained with the power consumption of 35.1 mW at 1.0 V supply voltage. The total chip area is 2.61 mm2

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Design of low power Wallace tree multiplier using modified full adder

2024-02-08 , Ahmad Fariz Hasan , Sohiful Anuar Zainol Murad , Faizah Abu Bakar , Husin M.F.C. , Sapawi R.

High speed and energy-efficient of a device are essential in the electronics industry due to the high demand for multimedia usage and fast technology. Multipliers play a vital role, especially in the processor's integrated circuits, microprocessors, filters, and arithmetic units. Wallace tree multiplier works in parallel, making it an efficient multiplier in terms of area and speed. Internally, a multiplier consists of Adder, which is full Adder (FA) and half Adder (HA). Full adders give a significant contribution to making a multiplier that works very well. A processor or chip performs very efficiently and effectively when running at high speed, in a small area, and at low power. Modification of full Adder in Wallace tree multiplier helps to consume low power during multiplication. In this project, 4-bit and 8-bit Wallace tree multipliers are designed. The design is developed in Verilog HDL and simulated the functionalities using Quartus II software. Mentor Graphic software was used to produce the final layout of 8 x 8-bit Wallace tree multiplier. The modified Wallace tree multiplier shows 64.97mW power lower than the conventional multiplier, which was 65.88mW.

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Publication

Design of High-Quality Factor Active Indictor Using CMOS 0.18-μm Technology for 5G Applications

2022-01-01 , Ali H.A.A.A. , Sohiful Anuar Zainol Murad , Ahmad Fariz Hasan , Faizah Abu Bakar , Sapawi R.

This paper presents high quality factor of active inductor circuit for 5G application. The proposed circuit is based on the differential active inductor (DAI) topology. The DAI is designed using CMOS 0.18 μm technology. The quality factor (Q) can be tuned with the current source values, ranging from 0.5 mA to 3 mA, while the voltage can control the inductance values L. Meanwhile, the frequency range can be controlled with the feedback resistance. The simulation results indicate that the Q factor as large as 262.5k can be achieved with inductor values of 10 nH at frequency 3.2 GHz. In addition, the Q factor of 1650 is obtained at 3.5 GHz. The performance comparison with previously published works is also demonstrated and found that the proposed DAI is suitable for 5G application.

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Development Of Smart Glove With Mobile App That Helps Normal People To Self-Learn Malaysian Sign Language

2022-11-01 , Shaharudin W.N.Q.W.M. , Zabidi M.I.Z.M. , Abidin A.F.Z. , Ahmad Fariz Hasan , Harun M.H. , Azahar A.H. , Salam S.

Sign language was used as a means of communicating many centuries ago. Learning sign language can be problematic and confusing for ordinary people, where most of them do not have the basics of the word. This paper aims to create a smart glove, which consists of a hardware-based glove complemented by a mobile application to help regular people learn Malaysian Sign Language (MSL) themselves. This differentiates this project compares to most other literature that focuses on translating MSL. The glove uses a microcontroller such as Arduino as a processor and an accelerometer as a sensor to recognize hand gestures defined by alphabet, number, and several Malaysian Sign Language words. The hand gesture data will be sent to the mobile application via Bluetooth communication. The mobile application built using MIT App Inventor will provide suitable questions and provide feedback to the user. In the result and discussion, the accuracy of the prototype is discussed. The effectiveness of the prototype as a learning tool is not discussed in this paper as the paper tries to fit within the scope of the journal. Having said that, the potential of the prototype for further improvement and a more detailed study from the perspective of learning theory needs to be studied to gauge accurately the effectiveness of the prototype as a learning tool

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Modified CMFB circuit with enhanced accuracy for data converter application

2013 , Mohd Fairus Ahmad , Sohiful Anuar Zainol Murad , Mukhzeer Mohamad Shahimin , Shamsul Amir Abdul Rais , Ahmad Fariz Hasan

Enhanced feedback voltage of common mode feedback (CMFB) circuit is designed in this work for CMOS data sampling application using 0.18-μm Silterra process technology. The double error detecting point circuit is employed to associate with the feedback point in order to prevent the undesired voltage common mode at the output of operational transconductance amplifier (OTA). The PMOS input transistor for injecting the common mode voltage is used to fit in the limitation of voltage division in low power design. The feedback voltage is strongly pushed to have a stable value as to make the outputs of differential amplifier circuit swing at a nearly constant voltage at 1.2 V for enhancing accuracy of data converter.

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A 28 GHz 0.18-μm CMOS cascade power amplifier with reverse body bias technique

2019-08-01 , Ahmad Fariz Hasan , Sohiful Anuar Zainol Murad , Faizah Abu Bakar

A 28 GHz power amplifier (PA) using CMOS 0.18 μm Silterra process technology is reported. The cascade configuration has been adopted to obtain high Power Added Efficiency (PAE). To achieve low power consumption, the input stage adopts reverse body bias technique. The simulation results show that the proposed PA consumes 32.03mW and power gain (S21) of 9.51 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 11.10 dBm and maximum PAE of 16.55% with output 1-dB compression point (OP1dB) 8.44 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.

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A 46% PAE, 2.4-GHz Two-Stage Class E Power Amplifier Utilizing CMOS 0.13-µm Technology

2024-01-01 , Sohiful Anuar Zainol Murad , Ahmad Fariz Hasan , Shaiful Nizam Mohyar

A wireless device with a long battery life and great sensitivity becomes difficult to develop since there is a huge demand for low-power, low-cost wireless gadgets. The power amplifier (PA) is the most crucial part of radio frequency (RF) transceivers because of its massive power consumption. Consequently, in order to minimize power loss, a very effective and low-power consumption PA is needed. In this paper, high efficiency two-stage CMOS PA designed in 0.13-μm process for 2.4 GHz IoT transmitter applications is presented. The driver stage and power stage are the two stages that make up the two-stage topology of the proposed CMOS PA. To attain high efficiency and great power gain, a class E PA is used at the power stage. The LC matching network at the output is used for harmonic rejection filter at 2.4 GHz with an additional parallel capacitor helps for better harmonic rejection. In addition, a layout has been successfully designed and optimized. All the components in the proposed PA are designed on-chip. The pre-layout and post-layout simulations have been conducted to verify the proposed PA's performance. The pre-layout simulation of the proposed PA can deliver 19.19 dBm output power and 45.2% PAE at 2.0 V power supply into a 50-Ω load. On the other hand, the proposed PA produced an output power of 17.33 dBm and 46% PAE, according to the results of the post-layout simulation with a similar power supply of 2.0 V. The chip area for the proposed layout design is 1.05 mm2.

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Design of High-Quality Factor Active Indictor Using CMOS 0.18-μm Technology for 5G Applications

2022-01-01 , Ali H.A.A.A. , Sohiful Anuar Zainol Murad , Ahmad Fariz Hasan , Faizah Abu Bakar , Sapawi R.

This paper presents high quality factor of active inductor circuit for 5G application. The proposed circuit is based on the differential active inductor (DAI) topology. The DAI is designed using CMOS 0.18 μm technology. The quality factor (Q) can be tuned with the current source values, ranging from 0.5 mA to 3 mA, while the voltage can control the inductance values L. Meanwhile, the frequency range can be controlled with the feedback resistance. The simulation results indicate that the Q factor as large as 262.5k can be achieved with inductor values of 10 nH at frequency 3.2 GHz. In addition, the Q factor of 1650 is obtained at 3.5 GHz. The performance comparison with previously published works is also demonstrated and found that the proposed DAI is suitable for 5G application.

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