Shaiful Nizam Mohyar
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Preferred name
Shaiful Nizam Mohyar
Official Name
Shaiful Nizam, Mohyar
Alternative Name
Mohyar, Shaiful Nizami
Mohyar, Saiful Nizam
Mohyar, S. N.
Mohyar, Shaiful Nizam
Mohyar, Shaiful N.
Main Affiliation
Scopus Author ID
55534021900
Researcher ID
FJX-6667-2022

Research Output
Now showing 1 - 2 of 2
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Publication

Design of a low-power CMOS operational amplifier with common-mode feedback for pipeline analog-to-digital converter applications

2017-01-01 , Sohiful Anuar Zainol Murad , Izatul Syafina Ishak , Mohd Fairus Ahmad , Shaiful Nizam Mohyar

This paper proposes a design of a low-power operational ampliér (op-amp) for pipeline analog-to-digital converter (ADC) applications using a 0.13-μm CMOS process. The folded-cascode topology with NMOS input types is employed for the op-amp design due to a larger output gain compared to PMOS input types. Furthermore, the op-amp is designed with a double detection structure of a common-mode feedback circuit to provide stable feedback voltage. The simulation results show that the proposed op-amp achieved a gain of 64.5 dB and a unity gain bandwidth of 695.1 MHz with a low power consumption of 0.14 mW. In addition, by applying ±1.2 V of input voltage, the output voltage generated by the proposed op-amp design remains at 1.2 V with a constant feedback voltage of 1.3 V. Moreover, the proposed circuit was implemented and simulated successfully in a 1.5-bit per stage pipeline ADC.

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Publication

Low noise figure 2.4 GHz down conversion CMOS mixer for wireless sensor network application

2017-01-06 , Sohiful Anuar Zainol Murad , Shaiful Nizam Mohyar , Azizi Harun , Mohd Najib Mohd Yasin , Izatul Syafina Ishak , Rohana Sapawi

This work proposed a low noise figure 2.4 GHz down-conversion CMOS mixer for wireless sensor network (WSN) application using 0.13-μm Silterra technology. The proposed down-conversion mixer converts a high radio frequency (RF) signal from 2.4 GHz to an intermediate frequency (IF) of 100 MHz through the use of a local oscillator signal (LO) of 2.3 GHz. The proposed mixer employs a double balance Gilbert-cell topology with integrated input matching at the input stage and a low pass filter at the IF stage. The simulation results indicate that the proposed mixer obtains lower noise figure (NF) of 5.21 dB with an input third-order intercept point (IIP3) of 0 dB. Furthermore, the conversion gain (CG) of 8.6 dB is achieved with the power consumption of 1.57 mW at 1.8 V supply voltage.

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