Ruzelita Ngadiran
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Preferred name
Ruzelita Ngadiran
Official Name
Ruzelita, Ngadiran
Alternative Name
Ngadiran, Ruzelita
Ngadiran, R.
Binti Ngadiran, Ruzelita
Main Affiliation
Scopus Author ID
36548898800
Researcher ID
ABF-3045-2020

Research Output
Now showing 1 - 4 of 4
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Publication

Tomato Diseases Classification Using Extreme Learning Machine

2023-10-06 , Xian T.S. , Ruzelita Ngadiran , Iszaidy Ismail , Amiza Amir , Siti Zuraidah Ibrahim , Taha T.B.

Plant disease classification is essential to the agriculture industry. In this work, a tomato disease classification using Extreme Learning Machine (ELM) with image-based features. Extreme Learning Machine (ELM), a classification algorithm with a single layer feed-forward neural network where it can be combined with few activation functions. The image features as the input where the image is pre-processed via HSV colour space and extracted using Haralick textures, colour moments and HSV histogram. The features are then loaded in the ELM classifier to perform the ELM training and testing. The accuracy result of ELM classification is then analysed after the validation. The dataset used for disease detection is tomato plant leaves which is a subset of the Plant-Village dataset. The results produced from the ELM demonstrate an accuracy of around 84.94% which is comparable to classifiers such as the Support Vector Machine and Decision Tree.

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Publication

Design and Implementation of Lifting Wavelet Transform Using Field Programmable Gate Arrays

2020-03-20 , Taha T.B. , Ruzelita Ngadiran , Phak Len Al Eh Kan

Lifting Wavelet transform (LWT) has an extensive usage in different image processing applications as image compression and information hiding. LWT is considered a good solution for hardware designs as it relies only on integer calculations while applying the wavelet transform. In this paper, an FPGA design and implementation of LWT is presented, the implementation is achieved using VHDL coding without importing off-shelf components which make the proposed design applicable to a wide range of devices. The design is based on parallel execution to perform LWT implementation with real time response. The design utilized 421 logic registers of DE2 Cyclone II (EP2C35F672C6) FPGA device with 151.91MHz frequency.

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Digital image watermarking algorithm based on texture masking model

2019-01-01 , Taha D.B. , Taha T.B. , Al Dabagh N.B. , Ruzelita Ngadiran , Ehkan P.

The trade-off between invisibility and robustness in image watermarking algorithms is considered as one of the major issues in designing watermark-based copyright protection systems. Accordingly, different models had been proposed in the literature to obtain robust watermarked images while maintaining the perceptual quality. However, most of these studies are involved with complex algorithms as using multiple signal transformation tools within hybrid systems. In this paper, a low complexity texture-masking model based on Lifting Wavelet Transform (LWT) is utilized to find the blocks with the highest texture and choose them for watermark embedding. Choosing highly textured places helps to insert the watermark with a further intensity that leads to higher robustness and at the same time the Human Visual System (HVS) is less sensitive to changes in these areas. As a result, high quality watermarked images were produced in terms of objective and subjective evaluations, as the structural similarity value (SSIM) for tested images was larger than 0.99.

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FPGA Implementation of High-Capacity SD Card using VHDL Language

2024-01-01 , Taha T.B. , Ruzelita Ngadiran , Phak Len Al Eh Kan

Limitations in capacity of internal memory chips on embedded systems lead to the usage of external memories especially when processing large amount of data as images or videos. FPGAs as embedded system devices used in different signal processing applications require extra memory for data storage. Current attempts in programming Secure Digital (SD) cards as external memories attached to FPGAs came with utilization of aiding application or of shelf tools which consumes large amount of chip clock cycles and reduce the overall performance. In this paper, a hardware implementation of SD card programming is presented by using pure and standalone VHDL code with high programming flexibility. In addition, High-Capacity SD cards (SDHC) are implemented for maximum storage capacity to handle large amount of data.

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