Browsing by Author "A Al-Khalidi"
  • Publication
    Heavily doped n++ GaN cap layer AlN-GaN metal oxide semiconductor high electron mobility transistor
    ( 2021-12)
    K Karami
    ;
    S Taking
    ;
    A Ofiare
    ;
    A Dhongde
    ;
    A Al-Khalidi
    ;
    E Wasige
    In this work, we report on the processing and device characteristics of n++ GaN/AlN/GaN metal oxide semiconductor high electron mobility transistors (MOSHEMTs). The AlN/GaN structure is capped with a highly doped n++ GaN layer which provides more free electrons in the cap layer thus helps in reducing the Ohmic contact resistance. However, this layer in the gate region needs to be removed prior to gate metal deposition to avoid a conducting path between gate metal and the cap layer. A conducting path between the gate metal and GaN cap layer creates gate to source and gate to drain short circuit. A selective etching recipe was developed between n++ GaN and AlN layers. The gas used is a mixture of SF6 and O₂. A 5 nm SiO₂ is used as a gate dielectric and surface passivation to the device. The fabricated device shows a maximum drain current density of 800 mA/mm and a maximum peak transconductance of 135 mS/mm. The breakdown voltage of the device is 73 V. The measured contact resistance for the non-annealed and annealed Ohmic contact is between 5 to 10 Ω.mm and 0.4 to 0.6 Ω.mm, respectively. This indicates that the usage of heavily doped 5 nm n++ GaN cap layer helps in reducing the contact resistance. The results show the potential of the AlN/GaN MOSHEMT structure with a n++ GaN cap layer for future high frequency power application.
  • Publication
    Investigation of plasma induced etch damage-changes in AlGaN-GaN HEMTs
    ( 2021-12)
    A Ofiare
    ;
    S Taking
    ;
    K Karami
    ;
    A. Dhongde
    ;
    A Al-Khalidi
    ;
    E Wasige
    In this work, we report on the processing and device characteristics of AlGaN/GaN HEMT devices to investigate the effects of silicon dioxide (SiO₂) etching using Fluoroform (CHF3) gas prior to gate metal deposition. Three different GaN device structures were fabricated: (a) device #1 in which the device passivation (using SiO₂) and gate metallisation are done inone lithography step, (b) device #2 in which the device passivation and gate metallizationare done in 2 separate steps, (c) device #3, in which the gate metallization is deposited priorto passivation. 100 nm of plasma enhanced chemical vapor deposition (PECVD) SiO₂ wasdeposited for surface passivation to the devices. As fabricated, devices #1 and #2 exhibitedvery poor device characteristics with very low output currents which we attribute to surfaceplasma induced damage or changes on the gate region after the SiO₂ etching. A two-steppost gate annealing step was performed on the devices to recover this damage. The highestmaximum drain current of over 1100 mA/mm was observed on device #3 after the firstanneal step compared to other devices which showed higher maximum drain current afterthe second anneal step. All three devices show an improvement in self-heating behavior afterthe second anneal step along with more stable transfer characteristics. The highestmaximum peak transconductance of over 250 mS/mm was observed on devices #2 and #3after the first anneal step. This reduces slightly for all devices but with more stablecharacteristics. The measured threshold voltage values (VTH) are also consistent and stableafter performing the second anneal step. These results indicate that avoiding exposing theactive region of GaN devices is important in achieving expected and stable characteristics. Italso observed that further device improvement can be done by performing a two-step postgate annealing process.