Two stage CMOS operational amplifier in 0.13?μm technology using pseudo cascode compensation

Various wireless, implantable and wearable devices are used for continuous monitoring of health condition. These devices consist of various type of biosensor such as pacemaker. The operational amplifier (op-amp) is an example of an extended device which is located at the front end of this biosensor. The op-amp plays an important role of amplifying the strength of a signal. This paper focuses on the development of a two stage CMOS op-amp in 0.13?μm technology using pseudo cascode compensation technique. The pseudo cascode compensation technology is proposed to enhance the stability of a circuit. The op-amp is implemented using 0.13?μm CMOS technology from Siltera (Malaysia) and is simulated using a Mentor Graphic Design Architect software package. The proposed op amp achieved DC gain of 57.87?dB, unity gain frequency of 57.390?kHz, bandwidth of 54.87?Hz and power dissipation of 3.02?mW for 50?μA external bias current. The op-amp shows exceptionally stable operation with phase margin of 80.65 ° and gain margin of 10.901?dB.