Siti Zarina Md Naziri
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Siti Zarina Md Naziri
Official Name
Siti Zarina, Md Naziri
Alternative Name
Naziri, S. Z.M.
Naziri, S. Z. M.
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Scopus Author ID
26428387900

Research Output

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  • Publication
    Image processing for paddy disease detection using K-means clustering and GLCM algorithm
    ( 2021-12)
    A. F. A. Ahmad Effendi
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Imran Ahmad
    ;
    Mohd Fikri Che Husin
    ;
    Siti Zarina Md Naziri
    The traditional human-based visual quality inspection approach in agriculture is unreliable and uneven due to various variables, including human errors. In addition to the lengthy processing durations, the traditional method necessitates plant disease diagnostic experts. On the other hand, existing image processing approaches in agriculture produce low-quality output images despite having a faster computation time. As a result, a more comprehensive set of image processing algorithms was used to improve plant disease detection. This research aims to develop an efficient method for detecting leaf diseases using image processing techniques. In this work, identifying paddy diseases based on their leaves involved a number of image-processing stages, including image pre-processing, image segmentation, feature extraction, and eventually paddy leaf disease classification. The proposed work targeted the segmentation step, whereby an input image is segmented using the K-Means clustering with image scaling and colour conversion technique in the pre-processing stage. In addition, the Gray Level Co-occurrence Matrix technique (GLCM) is used to extract the features of the segmented images, which are used to compare the images for classification. The experiment is implemented in MATLAB software and PC hardware to process infected paddy leaf images. Results have shown that K-Means Clustering and GLCM are capable without using the hybrid algorithm on each image processing phase and are suitable for paddy disease detection.
      1  74
  • Publication
    Design of multiplicative inverse value generator using logarithm method for AES algorithm
    ( 2020)
    Goh Yie Yen
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Advanced Encryption Standard (AES) algorithm is one of the most widely used symmetric block cipher that is utilized in data protection through symmetric cryptography algorithm, as it offers high efficiency and ability in securing information. In AES, the SubByte/InvSubByte transformation costs an amount of memories for the lookup tables (LUT) that leads to area usage in hardware. As per mathematical equations, the SubByte/InvSubByte is able to share the same resource which is the multiplicative inverse value table. Instead of using LUTs, the multiplicative inverse values can be generated on-the-fly as needed. Therefore, this paper presents the custom hardware design and implementation of multiplicative inverse value generator using logarithm method specifically for AES algorithm. The logarithm method benefits the usage of antilog and log values in obtaining the multiplicative inverse value. The EDA tools as Intel Quartus Prime, Synopsys Design Compiler and IC Compiler are used to perform functional simulation, on synthesis analysis and block-level implementation. Detailed comparison is made between this work and previous implementation. The newly designed multiplicative inverse value generator has achieved the improvement on speed and area as compared to previous implementation. The area of the design is reduced around 8.5% with current improvement of 63.091 μm2, while the speed has increased to 2.54 ns with a positive slack of 0.11 ns, which is shorter than the previous implementation. The new design also outreached the performance of the common LUT-based design. © 2020 IEEE.
      34  3
  • Publication
    Image data compression using fast Fourier transform (FFT) technique for wireless sensor network
    ( 2024-02-08)
    Haron M.H.
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Imran Ahmad
    ;
    Arshad M.A.M.
    ;
    Asral Bahari Jambek
    ;
    Siti Zarina Md Naziri
    ;
    Hussin R.
    ;
    Harun A.
    ;
    Rizalafande Che Ismail
    ;
    Shaiful Nizam Mohyar
    Agricultural settings present unique challenges for the transmission of huge amounts of images over long-range wireless networks. It is challenging to remotely gather data for transmission over a wireless network in research areas due to a lack of basic amenities like internet connections, especially in distant agricultural areas. In this research, the Fast Fourier Transform (FFT) method was used in conjunction with the Discrete Cosine Transform (DCT) method of image compression to achieve a higher compression ratio. In order for a Wireless Sensor Network (WSN) to provide compressed image data to a wireless based station, a LoRaWAN network has been identified. Low-power LoRaWAN networks may regularly transmit compressed images from an agricultural region to a monitoring system up to 15 km away. Images of golden apple snails were collected for this study from a variety of sources. The procedure was coded in MATLAB so that it could be run with input images being judged by the created algorithm. The input images can be compressed with a range of compression ratios (CR) from 3.00 to 50.00, as shown by the simulation results. Compressed image quality is measured not only by the above-mentioned criteria, but also by Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR). According to the numbers, the best achievable compression ratio is 49.04, with an MSE of 172.72 and a PSNR of 25.75 at its highest.
      29  4
  • Publication
    Face Recognition and Identification using Deep Learning Approach
    ( 2021)
    KH Teoh
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Razaidi Hussin
    ;
    Mohd Nazrin Md Isa
    ;
    Muhammad Sufyan Safwan Basir
    Human face is the significant characteristic to identify a person. Everyone has their own unique face even for twins. Thus, a face recognition and identification are required to distinguish each other. A face recognition system is the verification system to find a person’s identity through biometric method. Face recognition has become a popular method nowadays in many applications such as phone unlock system, criminal identification and even home security system. This system is more secure as it does not need any dependencies such as key and card but only facial image is needed. Generally, human recognition system involves 2 phases which are face detection and face identification. This paper describes the concept on how to design and develop a face recognition system through deep learning using OpenCV in python. Deep learning is an approach to perform the face recognition and seems to be an adequate method to carry out face recognition due to its high accuracy. Experimental results are provided to demonstrate the accuracy of the proposed face recognition system.
      2  21
  • Publication
    Area optimization of active reference band gap amplifier in cadence virtuoso
    ( 2024-02-08)
    Sheng T.W.
    ;
    Razaidi Hussin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    ;
    Norhawati Ahmad
    ;
    Muammar Mohamad Isa
    ;
    Afzan Kamarudin
    Band Gap Amplifier is mostly used in integrated circuit (IC) chips. It is commonly used to generate temperature independent reference voltage. Band Gap Amplifier is essential and implemented widely in analog and digital circuits because it is temperature independent thus produces low voltage. In this work, layout of active reference band gap amplifier is designed in cadence virtuoso and the percentages of differences sizes of layouts are compared. The different versions of layout design are compared in the result to show the percentages of area optimization. The main layout designs such as layout 1 (without sharing source, drain and well), layout 2 (sharing source, drain without sharing wells), and layout 3 (share the source, drain, and well) are designed to get the comparison of area optimization. The results show that there is 27.73% reduction overall layout by applied several techniques to optimize the area in layout design in order to get a compactable layout.
      6  35
  • Publication
    Hardware Design of Combinational 128-bit Camellia Symmetric Cipher using 0.18μm Technology
    (Institute of Electrical and Electronics Engineers Inc., 2022-01-01)
    Sak C.U.
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Camellia is another symmetric key block cipher with a 128-bit block size and key sizes of 128, 192, and 256 bits. As the hardware version of cipher implementation is getting popular, the Camellia hardware design should be constantly improved in terms of performance. The key aim of this research is to design and implement the improved version of Camellia cipher using custom-based approach based on 0.18μm technology. The new hardware Camellia design is synthesized using timing, area and power constraints to achieve less area, less power and high-speed design. Finally the results are been compared and analyzed with previous implementation in terms of performance parameters. The design is described using Verilog HDL and been verified using functional simulation from the Modelsim-Intel FPGA, while Synopsys had been utilized for synthesis process. Based on the generated synthesis reports, the total area consumed by the design on ASIC platform is 1294.11-unit area with a total cell area of 1176.25-unit area, while the total power consumption is 0.1245mW, and an increased speed of more than 80% as compared to previous design. In conclusion, this design had achieved better performance compared to previous design.
      2  6
  • Publication
    Speed and Area Efficient FXP Adders and Multipliers: A Comparative Analysis for LNS System
    ( 2020-12-18)
    Basir M.S.S.M.
    ;
    Rizalafande Che Ismail
    ;
    Siti Zarina Md Naziri
    ;
    Mohd Nazrin Md Isa
    ;
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    In this paper, a variety of adder and multiplier are compared to be implemented in a new logarithmic number system (LNS). Both adder and multiplier are designed with a generic very high-speed integrated circuit hardware description language (Verilog) program. This makes it possible to achieve the optimum performance in latency and area of 0.18µm CMOS technologies LNS chip. Consequently, the optimal configurations vary with speed and area of the schemes and in some cases can be compact area, O(n), fast in latency O(log2 n) or optimized. The program was scripted based on fixed-point (FXP) adders and multipliers that yet will be implemented in LNS system. The functionality of the scheme was tested before synthesized. Outcomes show that Ladner Fisher (LF) adder and modified Baugh Wooley multiplier contribute to fast in latency and consume minimal area.
      4  24
  • Publication
    An implementation of Short Time Fourier Transform for Harmonic Signal Detection
    ( 2021-03-01)
    Basir M.S.S.M.
    ;
    Rizalafande Che Ismail
    ;
    Yusof K.H.
    ;
    Katim N.I.A.
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    Power electronic components has the tendency to induce a non-linear signal called harmonic distortion. Without proper monitoring tools, harmonic distortion can harm sensitive electronic equipment, and in worse case scenarios, may lead to unreliable operation of controller and misalignment of motoring unit. This matter can be compromised by taking safety precaution, by identifying the level of harmonic rise in the electrical system. This paper presents analysis on different characteristics of harmonic signal using frequency distribution technique, namely Fourier transform (FT), and proposal of time-frequency distribution (TFD) technique, which is a short time Fourier transform (STFT). The novelty of utilizing STFT is the analyzed signal is represented in both time and frequency marginals, hence providing extra information of the spectral over the time. Simulation was carried out using MATLAB, by means the results consisting of the magnitude of multi-frequency components signal were represented in time-frequency representation (TFR). From the TFR, parameters such as instantaneous RMS fundamental voltage, V1RMS(t), instantaneous RMS voltage, VRMS(t), instantaneous total waveform distortion, VTWD(t), instantaneous total harmonic distortion, VTHD(t) and instantaneous total nonharmonic distortion, VTnHD(t) had been extracted. The performance of different harmonic signals such as normal, single-level harmonic, multi-level harmonic, short duration harmonic and interharmonic had been analyzed. The performance based on absolute percentage error (APE) index indicated average of 93% of correctness using 256 window length in STFT measurement.
      30  2
  • Publication
    Development of fruits artificial intelligence segregation
    ( 2021-12)
    Norhidayah Mohd Rozi
    ;
    Razaidi Hussin
    ;
    Muammar Mohamad Isa
    ;
    Syed Muhammad Mamduh Syed Zakaria
    ;
    Afzan Kamarudin
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Siti Zarina Md Naziri
    Higher output was needed as technology advance to meet human needs and industry demands. Fruits Artificial Intelligence Segregation (FAIS) is a project that uses image processing to detect and differentiate between various types of fruits. This paper proposes an OpenCV python, and the Convolution Neural Network (CNN) is used to complete the segregation of multiple fruits. The code extracts the fruit's characteristics and separates them based on their color and shape once placed in front of the camera to implement liveness detection. This paper shows the accuracy and reliability of the Fruits Artificial Intelligence Segregation (FAIS) system based on the number of datasets.
      1  25
  • Publication
    Hardware Design of Combinational 128-bit Camellia Symmetric Cipher using 0.18µm Technology
    ( 2022)
    Chawalit Udom Sak
    ;
    Siti Zarina Md Naziri
    ;
    Rizalafande Che Ismail
    ;
    Mohd Nazrin Md Isa
    ;
    Razaidi Hussin
    Camellia is another symmetric key block cipher with a 128-bit block size and key sizes of 128, 192, and 256 bits. As the hardware version of cipher implementation is getting popular, the Camellia hardware design should be constantly improved in terms of performance. The key aim of this research is to design and implement the improved version of Camellia cipher using custom-based approach based on 0.18µm technology. The new hardware Camellia design is synthesized using timing, area and power constraints to achieve less area, less power and high-speed design. Finally the results are been compared and analyzed with previous implementation in terms of performance parameters. The design is described using Verilog HDL and been verified using functional simulation from the Modelsim-Intel FPGA, while Synopsys had been utilized for synthesis process. Based on the generated synthesis reports, the total area consumed by the design on ASIC platform is 1294.11-unit area with a total cell area of 1176.25-unit area, while the total power consumption is 0.1245mW, and an increased speed of more than 80% as compared to previous design. In conclusion, this design had achieved better performance compared to previous design.
      3  19