Faizah Abu Bakar
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Preferred name
Faizah Abu Bakar
Official Name
Faizah, Abu Bakar
Alternative Name
Bakar, Faizah Abu
Bakar, F. A.
Main Affiliation
Scopus Author ID
36809027100
Researcher ID
DWO-5731-2022

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  • Publication
    A 28 GHz 0.18-μm CMOS cascade power amplifier with reverse body bias technique
    ( 2019-08-01)
    Ahmad Fariz Hasan
    ;
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    A 28 GHz power amplifier (PA) using CMOS 0.18 μm Silterra process technology is reported. The cascade configuration has been adopted to obtain high Power Added Efficiency (PAE). To achieve low power consumption, the input stage adopts reverse body bias technique. The simulation results show that the proposed PA consumes 32.03mW and power gain (S21) of 9.51 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 11.10 dBm and maximum PAE of 16.55% with output 1-dB compression point (OP1dB) 8.44 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.
      6  36
  • Publication
    A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications
    ( 2020-04-01)
    Hasan A.F.
    ;
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    ;
    Zulkifli T.Z.A.
    A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology for milimeter wave applications is reported. Maximizing the power added efficiency (PAE) and output power are achieved by optimize the circuit with power divider and cascade configuration. In addition, reverse body bias is also employed for realizing excellent PAE and power consumption. A three stage CMOS PA with power combiner is designed and simulated. The simulation results show that the proposed PA consumes 62.56 mW and power gain (S21) of 8.08 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 12.62 dBm and maximum PAE of 23.74% with output 1-dB compression point (OP1dB) 10.85 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.
      1  28
  • Publication
    Dual band low noise amplifier: A review analysis
    ( 2024-02-08)
    Azizan A.
    ;
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    ;
    Manaf A.A.
    This paper discusses a few earlier efforts in the field of multiband low noise amplifier design (LNA). This study will look at a variety of modern multiband LNA designs, focusing on four topologies: induction matching with notch filter, current reused with cascode, current reused with notch filter, and common source with external capacitor. Each architecture has its own set of benefits and drawbacks. In the future, it will be necessary to strike a balance between tradeoffs, eliminate drawbacks, and achieve optimal multiband LNA performance.
      24  2
  • Publication
    A 3.5 GHz hybrid CMOS class E power amplifier with reverse body bias design for 5G applications
    ( 2021-05-03)
    Ahmad Fariz Hasan
    ;
    Sohiful Anuar Zainol Murad
    ;
    Faizah Abu Bakar
    A 3.5 GHz CMOS power amplifier (PA) using 0.18 μm Silterra process technology for 5G applications is reported. The proposed circuit consists of two stages. In the first stage, a cascade topology is adopted with a reverse body bias technique to obtain high voltage gain and minimize the current to reduce the power consumption. Meanwhile, a class-E is use in the second stage to obtain high efficiency. The simulation results of propose PA indicate that 22.6 dB of peak power gain (S21), 8.2 dBm of saturated power (Psat) and 54.6% of power added efficiency (PAE) is achieve at 3.5 GHz. These results prove that the proposed PA is suitable for low band 5G applications.
      2  35