Research Output
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PublicationDesign of High-Quality Factor Active Indictor Using CMOS 0.18-μm Technology for 5G Applications( 2022-01-01)This paper presents high quality factor of active inductor circuit for 5G application. The proposed circuit is based on the differential active inductor (DAI) topology. The DAI is designed using CMOS 0.18 μm technology. The quality factor (Q) can be tuned with the current source values, ranging from 0.5 mA to 3 mA, while the voltage can control the inductance values L. Meanwhile, the frequency range can be controlled with the feedback resistance. The simulation results indicate that the Q factor as large as 262.5k can be achieved with inductor values of 10 nH at frequency 3.2 GHz. In addition, the Q factor of 1650 is obtained at 3.5 GHz. The performance comparison with previously published works is also demonstrated and found that the proposed DAI is suitable for 5G application.
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PublicationDual band low noise amplifier: A review analysis( 2024-02-08)This paper discusses a few earlier efforts in the field of multiband low noise amplifier design (LNA). This study will look at a variety of modern multiband LNA designs, focusing on four topologies: induction matching with notch filter, current reused with cascode, current reused with notch filter, and common source with external capacitor. Each architecture has its own set of benefits and drawbacks. In the future, it will be necessary to strike a balance between tradeoffs, eliminate drawbacks, and achieve optimal multiband LNA performance.
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PublicationHigh linearity multi-band CMOS low noise amplifier at 2.4/3.5 GHz for 4G/5G applications( 2024-02-08)This paper presents a high linearity multi-band CMOS low noise amplifier (LNA) at 2.4/3.5 GHz for wireless application. The proposed multi-band CMOS LNA is targeted for concurrent 2.4 GHz and 3.5 GHz bands for 4G and 5G wireless technology, respectively. A cascoded topology with bandpass and bandstop filter at the input is utilized to achieve multiple-band frequency at 2.4 GHz and 3.5 GHz. The LNA is implemented and simulated using CMOS 0.13 μm process in Cadence Virtuoso Analog Design Environment software. The simulation results indicate that the gain (S21) of 15 dB/11 dB with the third order intercept point (IIP3) of 2.04 dBm/3.80 dBm at 2.4 GHz/3.5 GHz frequencies are achieved. Meanwhile, the noise figure of 3.0 dB/3.6 dB is obtained with the power consumption of 35.1 mW at 1.0 V supply voltage. The total chip area is 2.61 mm2
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PublicationDesign of low power Wallace tree multiplier using modified full adder( 2024-02-08)High speed and energy-efficient of a device are essential in the electronics industry due to the high demand for multimedia usage and fast technology. Multipliers play a vital role, especially in the processor's integrated circuits, microprocessors, filters, and arithmetic units. Wallace tree multiplier works in parallel, making it an efficient multiplier in terms of area and speed. Internally, a multiplier consists of Adder, which is full Adder (FA) and half Adder (HA). Full adders give a significant contribution to making a multiplier that works very well. A processor or chip performs very efficiently and effectively when running at high speed, in a small area, and at low power. Modification of full Adder in Wallace tree multiplier helps to consume low power during multiplication. In this project, 4-bit and 8-bit Wallace tree multipliers are designed. The design is developed in Verilog HDL and simulated the functionalities using Quartus II software. Mentor Graphic software was used to produce the final layout of 8 x 8-bit Wallace tree multiplier. The modified Wallace tree multiplier shows 64.97mW power lower than the conventional multiplier, which was 65.88mW.
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PublicationA 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications( 2020-04-01)A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology for milimeter wave applications is reported. Maximizing the power added efficiency (PAE) and output power are achieved by optimize the circuit with power divider and cascade configuration. In addition, reverse body bias is also employed for realizing excellent PAE and power consumption. A three stage CMOS PA with power combiner is designed and simulated. The simulation results show that the proposed PA consumes 62.56 mW and power gain (S21) of 8.08 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 12.62 dBm and maximum PAE of 23.74% with output 1-dB compression point (OP1dB) 10.85 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.
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PublicationDesign of High-Speed Low Power CMOS Operational Amplifier Utilizing 0.18-µm Technology for ADC Applications( 2023-10-06)This paper presents a design of high-speed low power CMOS operational amplifier utilizing 0.18-µm technology for ADC applications. A folded cascode with PMOS configuration is chosen as a topology for the op-amp design which provides high-speed structure and more stable configuration compare to the other topologies. High-swing cascode current mirror is combined as a biasing circuit to provide proper voltage and stable output current for the op-amp structure. The proposed design is simulated in Cadence Virtuoso EDA tools software. The simulation results show the DC gain of 61.85 dB and phase margin (PM) of 88.34° with 0.5 pF load capacitor is achieved. Moreover, the slew rate and settling time of 120.125 V/µs and 20.3 ns are obtained, respectively. A low power consumption of 0.17 mW at supply voltage of 1.8 V indicates the low power is achieved in the circuit design. The proposed high speed low power CMOS op-amp is suitable for high-speed ADC applications.
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PublicationDesign of Internet of Things Based Air Pollution Monitoring System Using ThingSpeak and Blynk Application( 2021-07-26)This paper presents the design of an IoT based air pollution monitoring system to measure carbon dioxide gas, butane gas, humidity and temperature. The hardware consists of MQ-2 gas sensor, ESP8266 Wi-Fi module, DHT22 temperature and humidity sensors. Meanwhile, the software used in this prototype is the Arduino Integrated Development Environment (IDE) written in function C and C++. The monitoring system indicate air quality is below than 100 AQI for safety air quality and more than 200 AQI for hazardous air quality. The green LED illuminated indicates there is no hazardous gas detected. Meantime, when the butane gas or carbon dioxide gas is identified, the red LED is illuminated. All the data are sent through ThingSpeak and Blynk applications. In ThingSpeak and Blynk applications, the data are displayed and updated after detected by the sensors in every 15 seconds and 1 second. In the Blynk application, when the hazardous gas is detected, the Blynk application sends a notification to alert the users immediately.
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PublicationDesign of High-Quality Factor Active Indictor Using CMOS 0.18-μm Technology for 5G Applications( 2022-01-01)This paper presents high quality factor of active inductor circuit for 5G application. The proposed circuit is based on the differential active inductor (DAI) topology. The DAI is designed using CMOS 0.18 μm technology. The quality factor (Q) can be tuned with the current source values, ranging from 0.5 mA to 3 mA, while the voltage can control the inductance values L. Meanwhile, the frequency range can be controlled with the feedback resistance. The simulation results indicate that the Q factor as large as 262.5k can be achieved with inductor values of 10 nH at frequency 3.2 GHz. In addition, the Q factor of 1650 is obtained at 3.5 GHz. The performance comparison with previously published works is also demonstrated and found that the proposed DAI is suitable for 5G application.
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PublicationA 3.5 GHz hybrid CMOS class E power amplifier with reverse body bias design for 5G applications( 2021-05-03)A 3.5 GHz CMOS power amplifier (PA) using 0.18 μm Silterra process technology for 5G applications is reported. The proposed circuit consists of two stages. In the first stage, a cascade topology is adopted with a reverse body bias technique to obtain high voltage gain and minimize the current to reduce the power consumption. Meanwhile, a class-E is use in the second stage to obtain high efficiency. The simulation results of propose PA indicate that 22.6 dB of peak power gain (S21), 8.2 dBm of saturated power (Psat) and 54.6% of power added efficiency (PAE) is achieve at 3.5 GHz. These results prove that the proposed PA is suitable for low band 5G applications.
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PublicationA 28 GHz 0.18-μm CMOS cascade power amplifier with reverse body bias technique( 2019-08-01)A 28 GHz power amplifier (PA) using CMOS 0.18 μm Silterra process technology is reported. The cascade configuration has been adopted to obtain high Power Added Efficiency (PAE). To achieve low power consumption, the input stage adopts reverse body bias technique. The simulation results show that the proposed PA consumes 32.03mW and power gain (S21) of 9.51 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 11.10 dBm and maximum PAE of 16.55% with output 1-dB compression point (OP1dB) 8.44 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.
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