Browsing by Subject "128-bits AES Algorithm | FPGA | Keyword: VLC Technology | Single Computing Engine | Single processing"
  • Publication
    Design and Implementation of FPGA-based Single Computing Engine of VLC Image Transfer
    ( 2023-10-06)
    Ismail S.N.
    ;
    Rashidi C.B.M.
    ;
    Salih M.H.
    ;
    Mahrom N.
    This paper has proposed a single computing engine based on VLC technology for use in real-time to secured image of transmitter and receiver systems implemented on an FPGA in real time. It is proposed that a single computing engine system consist of the following components be implemented: UART control, FIFO buffer, VGA controller, and 128-bits AES algorithm decryption and encryption. An Altera DE1-SoC board is used to implement the design, coded in VHDL, and implemented in Quartz prime 15.1 FPGA using a software platform system architecture. The single computing engine communication via VLC system hardware provides the highest security benefit with excellent image quality and unnoticeable local area communication security features. It has been demonstrated through implementation results that the single computing engine can operate at a maximum clock frequency of Fmax 170.97 MHz and achieve a throughput of 1.367 Mbps with the design single computing engine.