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  5. Development of varied CMOS ring oscillator topologies in 0.13-μm CMOS technology
 
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Development of varied CMOS ring oscillator topologies in 0.13-μm CMOS technology

Journal
Applied Mechanics and Materials
ISSN
1662-7482
Date Issued
2013
Author(s)
Sohiful Anuar Zainol Murad
Universiti Malaysia Perlis
Mohamad Shahimin Mukhzeer
Universiti Malaysia Perlis
Rizalafande Che Ismail
Universiti Malaysia Perlis
Mohd Fairus Ahmad
Universiti Malaysia Perlis
Sapawi Rohana
DOI
10.4028/www.scientific.net/AMM.446-447.882
Handle (URI)
https://hdl.handle.net/20.500.14170/13665
Abstract
This paper presents varied CMOS ring oscillator topologies using Silterra 0.13-µm Process. Three topologies of ring oscillators have been designed which is the single-ended ring oscillator, differential ring oscillator and ring oscillator based variable resistor for 2.4 GHz wireless applications. The proposed designs consist of five stages delay cell. The simulation results show that a single-ended ring oscillator obtained the lowest power consumption of 0.41 mW, while differential oscillator achieves phase noise of −64.44 dBc/Hz at 1 MHz offset frequency. However, ring oscillator based variable resistor did not achieve any significant improvement. The proposed design is oscillates at 2.4 GHz.
Subjects
  • Delay cell

  • Phase noise

  • Ring oscillator

  • Variable resistor

File(s)
Development of varied CMOS ring oscillator topologies in 0.13-μm CMOS technology.pdf.crdownload (260.42 KB)
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