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An extensive study on different underlap architectures for improved analog/RF performance of 32 nm DG-MOSFET

Journal
International Journal of Nanoelectronics and Materials (IJNeaM)
ISSN
1985-5761
Date Issued
2019-01
Author(s)
Avtar Singah
Invertis University, Bareilly
Arpan Dasgupta
University of California, Los Angeles
Rahul Das
Jadavpur University, Kolkata
Atanu Kundu
Heritage Institute of Technology, Kolkata
Saurabh Chaudhury
NIT Silchar, Silchar, Assam,India
Handle (URI)
https://ijneam.unimap.edu.my/
https://ijneam.unimap.edu.my/images/PDF/Jan%202019/Vol_12_No_1_2019_9_75-84.pdf
https://hdl.handle.net/20.500.14170/16041
Abstract
This paper proposed an underlap double-gate MOSFET (U-DG MOSFET) structure with gate stacking. Better sub-threshold slope and RF performance can be obtained from DG MOSFET with symmetrical/asymmetrical drain-source configuration. Simulation shows better results for its upgraded resilient against short channel effects (SCE). The analog and RF performances at 32 nm technology were estimated. Furthermore, the drive capability (on current) of the device, the intrinsic gain (gₘRₒ), the transconductance (gₘ), and transconductance generation factor (gₘ/Id) were also evaluated. By using non-quasi-static approach, high frequency parameters such as intrinsic (Cgs and Cgd), parasitic resistance (Rgs and Rgd), transport delay (τₘ), the unity gain cut-off frequency (fₜ), and the maximum frequency of oscillation (fₘₐₓ) were also calculated. A single stage amplifier was then designed to evaluate the performance of the proposed device.
Subjects
  • Underlap

  • Asymmetric structure

  • Analog performance

  • RF performance

  • Single stage amplifie...

File(s)
An Extensive Study on Different Underlap (1.36 MB)
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