Mohd Nazri Mohd Warip
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Preferred name
Mohd Nazri Mohd Warip
Official Name
Mohd Nazri , Mohd Warip
Alternative Name
Mohd Warip, Mohd Nazri
Mohd Warip, M. N.
Warip, M. N.
Warip, Mohd Nazri Mohd
Warip, Mohd Nazri bin Mohd
Main Affiliation
Scopus Author ID
36555091900
Researcher ID
EDT-8958-2022

Research Output

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Imporved MPR selection algorithm-based WS-OLSR routing protocol

2024-05-01 , Ahmed W.K. , Mohd Nazri Mohd Warip , Mohamed Elshaikh Elobaid Said Ahmed , Phak Len Al Eh Kan

Vehicle Ad Hoc Networks (VANETs) have become a viable technology to improve traffic flow and safety on the roads. Due to its effectiveness and scalability, the Wingsuit Search-based Optimised Link State Routing Protocol (WS-OLSR) is frequently used for data distribution in VANETs. However, the selection of MultiPoint Relays (MPRs) plays a pivotal role in WS-OLSR’s performance. This paper presents an improved MPR selection algorithm tailored to WS-OLSR, designed to enhance the overall routing efficiency and reduce overhead. The analysis found that the current OLSR protocol has problems such as redundancy of HELLO and TC message packets or failure to update routing information in time, so a WS-OLSR routing protocol based on improved-MPR selection algorithm was proposed. Firstly, factors such as node mobility and link changes are comprehensively considered to reflect network topology changes, and the broadcast cycle of node HELLO messages is controlled through topology changes. Secondly, a new MPR selection algorithm is proposed, considering link stability issues and nodes. Finally, evaluate its effectiveness in terms of packet delivery ratio, end-to-end delay, and control message overhead. Simulation results demonstrate the superior performance of our improved MR selection algorithm when compared to traditional approaches.

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Comparing and Assessing the Enhancements of DYMO and OLSR in VANETs

2020-09-21 , Khalid Ahmed W. , Mohd Nazri Mohd Warip , Khalid Abduljabbar W. , Mohamed Elshaikh Elobaid Said Ahmed

The main aspect of this work is to study the differences and define the behaviour of two different routing protocols. The first side is Dynamic MANETs On- Demand (DYMO) while the other side is proactive, optimal link-state routing (OLSR) and both the first and second are interactive routing protocols in the Ad-hoc network (VANET). The efficiency of these protocols was analysed and studied based on the use of three performance indicators: PDR, normal load (NRO) and end-to-end de1ay (E2ED) on the ability to change the size of different nodes. Omnet ++ was used by the INET Framework. We also used the SUMO simulation tool to build random movement patterns for VANET. From full simulation, we noticed that OLSR is doing better than DYMO for VANET at a price. Late and, as a result, the development of OLSR work in VANETs compared to DYMO, packet receipt ratios (PDR), side-to-side delay, normal path load, and VANETs.

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Comparative Study of Parallelism and Pipelining of RGB to HSL Colour Space Conversion Architecture on FPGA

2020-03-20 , Pakhlen Ehkan , Siew, Soon Voon , Fazrul Faiz Zakaria , Mohd Nazri Mohd Warip , Mohd Zaizu Ilyas

RGB colour model is a basic colour model and complements together to produce full colour range but it is unable to produce sufficient information for digital image analysis. However, HSL is capable to provide other useful information such as colour in degree, saturation of the colour and brightness of colour. In this work, RGB to HSL mathematical conversion algorithm is implemented on FPGA chip. Parallelism and pipelining capabilities of FPGA helps to speed up conversion performance. The RGB to HSL equation is implemented by using two architectures which are parallel and 7-stages pipeline architectures. The designed parallel and pipeline converters have one clock and seven clock cycle of data latency respectively. The parallel and pipeline architectures for RGB to HSL converter have been achieved rate of accuracy by hardware verification up to 99% and 98% and possessed maximum operating frequency merit of 50 MHz and 120 MHz respectively.

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Hyper-threading technology: Not a good choice for speeding up CPU-bound code

2017-01-03 , Ng Hui Qun , Zahereel Ishwar Abdul Khalib , Mohd Nazri Mohd Warip , Mohamed Elshaikh Elobaid Said Ahmed , Mostafijur R. , Nik Adilah Hanin Zahri , Puteh Saad

Hyper-threading (HT) technology allows one thread to execute its task while another thread is stalled waiting for shared resource or other operations to complete. Thus, this reduces the idle time of a processor. If HT is enabled, an operating system would see two logical cores per each physical core. This gives one physical core the ability to run two threads simultaneously. However, it does not necessarily speed up the performance of a parallel code twice the number of physical cores. This happens when two threads are trying to access the shared CPU resource. The instructions could only be executed one after another at any given time. In this case, parallel CPU-bound code could attain a little improvement in terms of speedup from HT on a quad-core platform, which is Intel i5-2410M@2.30GHz.

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Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

2017-06-01 , Ng Yen Phing , Mohd Nazri Mohd Warip , Phak Len Al Eh Kan , Farah W. Zulkefli , R Badlishah Ahmad

In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as a design solution to System-on-Chip (SoC). The routing algorithm, topology and switching technique are significant because of the most influential effect on the overall performance of Network-on-Chip (NoC). Designing of large scale topology alongside the support of deadlock free, low latency, high throughput and low power consumption is notably challenging in particular with expanding network size. This paper proposed an 8x8 XX-Torus and 64 nodes XX-Ring topology schemes for Network-on-Chip to minimize the latency by decrease the node diameter from the source node to destination node. Correspondingly, we compare in differences on the performance of mesh, full-mesh, torus and ring topologies with XX-Torus and XX-Ring topologies in term of latency. Results show that XX-Ring outperforms the conventional topologies in term of latency. XX-Ring decreases the average latency by 106.28%, 14.80%, 6.7 1%, 1.73%, 442.24% over the mesh, fully-mesh, torus, XX-torus, and Ring topologies.

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Toward Adaptive and Scalable Topology in Distributed SDN Controller

2023-03-01 , Kelian V.H. , Mohd Nazri Mohd Warip , R Badlishah Ahmad , Phak Len Al Eh Kan , Fazrul Faiz Zakaria , Mohd Zaizu Ilyas

The increasing need for automated networking platforms like the Internet of Things, as well as network services like cloud computing, big data applications, wireless networks, mobile Internet, and virtualization, has driven existing networks to their limitations. Software-defined network (SDN) is a new modern programmable network architectural technology that allows network administrators to control the entire network consistently and logically centralized in software-based controllers and network devices become just simple packet forwarding devices. The controller that is the network's brain, is mostly based on the OpenFlow protocol and has distinct characteristics that vary depending on the programming language. Its function is to control network traffic and increase network resource efficiency. Therefore, selecting the right controllers and monitoring their performance to increase resource usage and enhance network performance metrics is required. For network performance metrics analysis, the study proposes an implementation of SDN architecture utilizing an open-source OpenDaylight (ODL) distributed SDN controller. The proposed work evaluates the deployment of distributed SDN controller performance on three distinct customized network topologies based on SDN architecture for node-to-node performance metrics such as delay, throughput, packet loss, and bandwidth use. The experiments are conducted using the Mininet emulation tool. Wireshark is used to collect and analyse packets in real-time. The results obtained from the comparison of networks are presented to provide useful guidelines for SDN research and deployment initiatives.

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The impact of inner-parameters B-MAC protocol by Taguchi method for WSN

2020-03-15 , Yousif A.K. , Mohd Nazri Mohd Warip , Mohamed Elshaikh Elobaid Said Ahmed

The MAC protocols play an important role in the performance of wireless sensor network (WSN). MAC protocols are controlled with set of parameters from being dragged to undesired situation such as reduce the power consumption, listening idle, and overhead. This inner- parameters have direct impact on the efficiency of a MAC protocols and overall network performances. The impacts of theses parameters on reduce the power consumption are less considered. In the literature, a lot of studies concentrates on introducing a new protocols to reduce the power consumption for WSN. This paper aims to analysis the inner- parameters of MAC protocols for WSN power consumption by using Taguchi Delta Analysis (TDA). Moreover, the measure of inner - parameters is very important to find the optimal values to reduce the power consumption. This paper utilized Taguchi method to analysis the impact of B-MAC protocol parameters in WSN scenarios by exploits Taguchi delta analysis. Further, four inner - parameters are investigated in a simulation platform. Moreover, simulation experiments are carried out by OMNET++5 to prove the work in this paper. The obtained results show that inner- parameters B-MAC inner- protocol reduce the power consumption of WSN for two different scenarios.

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Deep-Learning Assisting Cerebral Palsy Patient Handgrip Task Translation

2021-07-26 , Fazrul Faiz Zakaria , Mohd Nazri Mohd Warip , Phaklen Ehkan , Muslim Mustapa , Mohd Zaizu Ilyas

An electro-encephalography (EEG) brain-computer interface (BCI) can provide the brain and external environment with separate information sharing and control networks. EEG impulses, though, come from many electrodes, which produce different characteristics, and how the electrodes and features to enhance classification efficiency have been chosen has become an urgent concern. This paper explores the deep convolutional neural network architecture (CNN) hyper-parameters with separating temporal and spatial filters without any pre-processing or artificial extraction processes. It selects the raw EEG signal of electrode pairs over the cortical area as hybrid samples. Our proposed deep-learning model outperforms other neural network models previously applied to this dataset in training time (∼40%) and accuracy (∼6%). Besides, considerations such as optimum order for EEG channels do not limit our model, and it is patient-invariant. The impact of network architecture on decoder output and training time is further discussed.

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Deep Learning with FPGA: Age and Gender Recognition for Smart Advertisement Board

2023-10-06 , Yeoh W.S. , Fazrul Faiz Zakaria , Mustapa M. , Mohd Nazri Mohd Warip , Phak Len Al Eh Kan , Mozi A.M.

Age and gender recognition are helpful in various applications, especially in the field of advertising. To replace the traditional advertising method that can only display the same contents to all audiences, a smart advertisement board capable of detecting age and gender of audiences to display relevant contents is required to increase the effectiveness of advertising. This paper will use two image datasets to train and test the Convolutional Neural Network (CNN) based architecture models for age and gender recognition using deep learning. The dataset that produced the best performing model will be implemented on three different devices to observe the performance of the models on each device. A gender recognition model with accuracy of 91.53% and age recognition model with accuracy of 59.62% is produced. The results have also shown the use of Field Programmable Gated Array (FPGA) has greatly boosted the performance of the models in terms of throughput and latency.

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Tuberculosis Classification Using Deep Learning and FPGA Inferencing

2023-02-01 , Fazrul Faiz Zakaria , Asral Bahari Jambek , Norfadila Mahrom , Rafikha Aliana A Raof , Mohd Nazri Mohd Warip , Al Eh Kan P.L. , Mustapa M.

Among the top 10 leading causes of mortality, tuberculosis (TB) is a chronic lung illness caused by a bacterial infection. Due to its efficiency and performance, using deep learning technology with FPGA as an accelerator has become a standard application in this work. However, considering the vast amount of data collected for medical diagnosis, the average inference speed is inadequate. In this scenario, the FPGA speeds the deep learning inference process enabling the real-time deployment of TB classification with low latency. This paper summarizes the findings of model deployment across various computing devices in inferencing deep learning technology with FPGA. The study includes model performance evaluation, throughput, and latency comparison with different batch sizes to the extent of expected delay for real-world deployment. The result concludes that FPGA is the most suitable to act as a deep learning inference accelerator with a high throughput-to-latency ratio and fast parallel inference. The FPGA inferencing demonstrated an increment of 21.8% in throughput while maintaining a 31% lower latency than GPU inferencing and 6x more energy efficiency. The proposed inferencing also delivered over 90% accuracy and selectivity to detect and localize the TB.

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