Amiza Amir
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Amiza Amir
Official Name
Amiza, Amir
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Scopus Author ID
36170326400
Researcher ID
EKV-8568-2022

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A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform

2023-01-01 , Mohammed N.Q. , Amiza Amir , R Badlishah Ahmad , Salih M.H. , Arrfou H. , Thalji N. , Matem R. , Abbas J.K.K. , Hussien Q.M. , Abdulhassan M.M.

High-security cryptography algorithms like AES require high computational capabilities to achieve information security. Therefore, it is necessary to use parallel computing architectures that exploit modern technologies to obtain the most conceivable computational power. Various methods have been introduced to achieve parallel processing. One of them is field-programmable gate arrays (FPGAs), which have good characteristics suitable for implementing parallel architectures with lower power consumption. This paper will focus on the most important FPGA boards that were used to implement the AES cryptographic algorithm. In addition, it demonstrates the general scheme of building architecture with multiple computing processing engines to get high performance and better throughput, which is reflected in the reduced cost and energy consumption of IoT devices.

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Design of Passive RFID Tag Using Frequency Selective Surface with Polarization Insensitive

2023-10-06 , Saidatul Norlyana Azemi , Ibrahim N.A. , Amiza Amir , Mohd Rashidi Che Beson , Abdul Aziz M.E.

RFID is not a new technology. It has been applied in various industries such as for wearable applications. Common RFID tags especially for those that have been designed and are available are not independent of the incident receiver angle. Numerous wearable antennas on the market are only designed for a certain received angle. For example, a wearable RFID antenna is used in medical as a pulse reading detector. If the patient makes any movement, the patient's pulse reading is no longer accurate or there may be no pulse reading. Hence, the purpose of this project is to design and RFID antennas using Frequency Selective Surface, FSS for wearable applications that are independent towards the incident angle and small in size. In this project, several antennas design with Frequency Selective Surface (FSS) is proposed. The design for this antenna is round, square, and hexagonal. This antenna has an operating frequency from 2.4 GHz to 5.8GHz, bandwidth efficiency> 50%, dielectric constant 1.30, independent incident angle up to 60 degrees, and has a high gain of around 2 to 3dB.

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Gain Enhancement of CPW Antenna for IoT Applications using FSS with Miniaturize Unit Cell

2021-07-26 , Saidatul Norlyana Azemi , Mohd Rashidi Che Beson , Amiza Amir , Azhari M.S.B.A. , Jiunn N.K.

Wireless connectivity is a critical enabler for many IoT applications. Antennas are often required to be installed inside the device cover, which usually occurs in small sizes with optimal performance. On the other hand, a suitable antenna should also have high efficiency, gain and adequate bandwidth covering the desired frequency range. Here, we proposed new type of Frequency Selective Surface (FSS) with miniaturized resonator element to enhance the gain of an CPW antenna. Furthermore, the miniaturization of the Frequency Selective Surface unit cell is attained by coupling the two meandered wire resonators. The wire resonator is separated by thin and single substrate layer. The structure of the FSS is shown to have a FSS unit cell dimension that is miniaturized to 0.057λ. The CPW antenna size is only 28.8mm × 46.5mm operating at 2.45 GHz frequency. With the additional of the FSS, the antenna's gain reaches up from 1.8 dBi to 2.6 dBi with omnidirectional radiation pattern.

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The Performance Analysis of K-Nearest Neighbors (K-NN) Algorithm for Motor Imagery Classification Based on EEG Signal

2017-12-11 , Nurul E’zzati Md Isa , Amiza Amir , Mohd Zaizu Ilyas , Mohammad Shahrazel Razalli

Most EEG-based motor imagery classification research focuses on the feature extraction phase of machine learning, neglecting the crucial part for accurate classification which is the classification. In contrast, this paper concentrates on the classifier development where it thoroughly studies the performance analysis of k-Nearest Neighbour (k-NN) classifier on EEG data. In the literature, the Euclidean distance metric is routinely applied for EEG data classification. However, no thorough study has been conducted to evaluate the effect of other distance metrics to the classification accuracy. Therefore, this paper studies the effectiveness of five distance metrics of k-NN: Manhattan, Euclidean, Minkowski, Chebychev and Hamming. The experiment shows that the distance computations that provides the highest classification accuracy is the Minkowski distance with 70.08%. Hence, this demonstrates the significant effect of distance metrics to the k-NN accuracy where the Minknowski distance gives higher accuracy compared to the Euclidean. Our result also shows that the accuracy of k-NN is comparable to Support Vector Machine (SVM) with lower complexity for EEG classification.

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Tomato Diseases Classification Using Extreme Learning Machine

2023-10-06 , Xian T.S. , Ruzelita Ngadiran , Iszaidy Ismail , Amiza Amir , Siti Zuraidah Ibrahim , Taha T.B.

Plant disease classification is essential to the agriculture industry. In this work, a tomato disease classification using Extreme Learning Machine (ELM) with image-based features. Extreme Learning Machine (ELM), a classification algorithm with a single layer feed-forward neural network where it can be combined with few activation functions. The image features as the input where the image is pre-processed via HSV colour space and extracted using Haralick textures, colour moments and HSV histogram. The features are then loaded in the ELM classifier to perform the ELM training and testing. The accuracy result of ELM classification is then analysed after the validation. The dataset used for disease detection is tomato plant leaves which is a subset of the Plant-Village dataset. The results produced from the ELM demonstrate an accuracy of around 84.94% which is comparable to classifiers such as the Support Vector Machine and Decision Tree.

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Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

2022-01-01 , Mohammed N.Q. , Amiza Amir , Salih M.H. , R Badlishah Ahmad

Applications, such as Internet of Things, deal with huge amount of transmitted, processed and stored images that required a high computing capability. Therefore, there is a need a computing architecture that contribute in increasing the throughput by exploiting modern technologies in both spatial and temporal parallelisms. This paper conducts a parallel quad-engine cybersecurity architecture with new configuration to increase the throughput. using DE1-SoC and Neek FPGA boards and HDL. In this architecture, each engine operates with 600MHz maximum frequency. Each image is divided into four parts of equal size and each part processed by single engine concurrently to achieve spatial parallelism. Internally, engine is handling image’s part in temporal parallelism and deep pipelining abstraction applied in every engine by dividing it to sub modules to execute different tasks concurrently. All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture. The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of processing

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Performance Analysis of Congestion Control Mechanism in Software Defined Network (SDN)

2017-12-11 , Rahman M.Z.A. , Naimah Yaakob , Amiza Amir , R Badlishah Ahmad , Yoon See Ki , Abd Halim A.H.

In the near future, the traditional networks architecture will be difficult to be managed. Hence, Software Defined Network (SDN) will be an alternative in the future of programmable networks to replace the conventional network architecture. The main idea of SDN architecture is to separate the forwarding plane and control plane of network system, where network operators can program packet forwarding behaviour to improve the network performance. Congestion control is important mechanism for network traffic to improve network capability and achieve high end Quality of Service (QoS). In this paper, extensive simulation is conducted to analyse the performance of SDN by implementing Link Layer Discovery Protocol (LLDP) under congested network. The simulation was conducted on Mininet by creating four different fanout and the result was analysed based on differences of matrix performance. As a result, the packet loss and throughput reduction were observed when number of fanout in the topology was increased. By using LLDP protocol, huge reduction in packet loss rate has been achieved while maximizing percentage packet delivery ratio.

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On the effectiveness of congestion control mechanisms for remote healthcare monitoring system in IoT environment - A review

2017-01-03 , Wan Aida Nadia Wan Abdullah , Naimah Yaakob , R Badlishah Ahmad , Amiza Amir , Siti Asilah Yah

A progressive advancement in biosensors and wireless technology are the major contributors to the realization of continuous remote health monitoring system (RHMS). Wireless Body Area Network (WBAN) is part of this technology due to the deployment of multiple sensors such as Electrocardiogram (ECG) to collect vital body signals for processing and diagnosis. Among the benefits offered by this technology include remote monitoring of patient's health status and early detection of abnormalities in the collected signals. Once detected, several preventive measurements can be taken. However, this system needs to encounter some challenges in the wireless network such as delay, packet loss and throughput due to network congestion when transmitting and receiving a bulk of multiple data. Generally, the presence of these problems in transmitting vital body signals may result in incorrect medical diagnosing which can increase mortality rate and cause severe impact to the overall system's performance. Thus, a suitable design of congestion control mechanism is urgently needed in designing a reliable and efficient remote health monitoring system.

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Controller Placement Algorithms in Software Defined Network - A Review of Trends and Challenges

2017-12-11 , Si-Kee Yoon , Zahereel Ishwar Abdul Khalib , Naimah Yaakob , Amiza Amir

Traditional network architectures are complex to manage, comparatively static, rigid and difficult to make changes for new innovation. The proprietary devices in such architectures are based on manual configuration which are unwieldy and error-prone. Software Defined Network (SDN) which is described as a new network paradigm that decouple the control plane from data plane are capable to solve today's network issues and improve the network performance. Nevertheless, among so many challenges and research opportunity in SDN, Controller Placement Problem (CPP) is said to be the most important issues which can directly affect the overall network performance. Thus far, the issue regarding the CPP and its challenge has not been completely reviewed and discussed properly in any other papers. In this paper, we provide a comprehensive review on several optimized controller placement problem algorithms in SDN. This paper also highlights some limitations of the reviewed methods and also emphasizes on suitable approach to address the aforementioned problems.

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Implementation Dual Parallelism Cybersecurity Architecture on FPGA

2022-05-01 , Mohammed N.Q. , Amiza Amir , Salih M.H. , Arrfou H. , Hussein Q.M. , R Badlishah Ahmad

This paper presents an efficient parallelism architecture that uses a dual-computing engine architecture to better throughput using both spatial and temporal parallelism on FPGA technology. This architecture will enhance the performance in terms of operating frequency and throughput and reduces the power consumption that meets applications with huge data processing such as Internet of Things in this design, two boards are used, "DE1_Soc and NEEK board" with Altera Quartus Prime 18 for synthesis and simulation. The proposed design architecture gives better resource usage and throughput through fewer hardware redundancies using a frequency of 600MHZ with 64 bits for each engine from the dual-engine. Furthermore, the proposed architecture implementation results show the reduction in the time delay by 40 % and achieves a throughput of 153.6 Gb/s.

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