Shaiful Nizam Mohyar
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Preferred name
Shaiful Nizam Mohyar
Official Name
Shaiful Nizam, Mohyar
Alternative Name
Mohyar, Shaiful Nizami
Mohyar, Saiful Nizam
Mohyar, S. N.
Mohyar, Shaiful Nizam
Mohyar, Shaiful N.
Main Affiliation
Scopus Author ID
55534021900
Researcher ID
FJX-6667-2022

Research Output
Now showing 1 - 3 of 3
  • Publication
    Design of a low-power CMOS operational amplifier with common-mode feedback for pipeline analog-to-digital converter applications
    ( 2017-01-01)
    Sohiful Anuar Zainol Murad
    ;
    Izatul Syafina Ishak
    ;
    Mohd Fairus Ahmad
    ;
    Shaiful Nizam Mohyar
    This paper proposes a design of a low-power operational ampliér (op-amp) for pipeline analog-to-digital converter (ADC) applications using a 0.13-μm CMOS process. The folded-cascode topology with NMOS input types is employed for the op-amp design due to a larger output gain compared to PMOS input types. Furthermore, the op-amp is designed with a double detection structure of a common-mode feedback circuit to provide stable feedback voltage. The simulation results show that the proposed op-amp achieved a gain of 64.5 dB and a unity gain bandwidth of 695.1 MHz with a low power consumption of 0.14 mW. In addition, by applying ±1.2 V of input voltage, the output voltage generated by the proposed op-amp design remains at 1.2 V with a constant feedback voltage of 1.3 V. Moreover, the proposed circuit was implemented and simulated successfully in a 1.5-bit per stage pipeline ADC.
  • Publication
    A very low-dropout voltage regulator in 0.18-μm CMOS technology for power management system
    ( 2020-07-01)
    Sohiful Anuar Zainol Murad
    ;
    Azizi Harun
    ;
    Mohd Nazrin Md Isa
    ;
    Shaiful Nizam Mohyar
    ;
    Karim J.
    A low dropout (LDO) voltage regulator is a type of voltage regulator circuit that works well even when the output voltage is very close to the input voltage, improving its power efficiency. This paper proposes the LDO voltage regulator in 0.18-μm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.
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  • Publication
    A 46% PAE, 2.4-GHz Two-Stage Class E Power Amplifier Utilizing CMOS 0.13-µm Technology
    ( 2024-01-01)
    Sohiful Anuar Zainol Murad
    ;
    Ahmad Fariz Hasan
    ;
    Shaiful Nizam Mohyar
    A wireless device with a long battery life and great sensitivity becomes difficult to develop since there is a huge demand for low-power, low-cost wireless gadgets. The power amplifier (PA) is the most crucial part of radio frequency (RF) transceivers because of its massive power consumption. Consequently, in order to minimize power loss, a very effective and low-power consumption PA is needed. In this paper, high efficiency two-stage CMOS PA designed in 0.13-μm process for 2.4 GHz IoT transmitter applications is presented. The driver stage and power stage are the two stages that make up the two-stage topology of the proposed CMOS PA. To attain high efficiency and great power gain, a class E PA is used at the power stage. The LC matching network at the output is used for harmonic rejection filter at 2.4 GHz with an additional parallel capacitor helps for better harmonic rejection. In addition, a layout has been successfully designed and optimized. All the components in the proposed PA are designed on-chip. The pre-layout and post-layout simulations have been conducted to verify the proposed PA's performance. The pre-layout simulation of the proposed PA can deliver 19.19 dBm output power and 45.2% PAE at 2.0 V power supply into a 50-Ω load. On the other hand, the proposed PA produced an output power of 17.33 dBm and 46% PAE, according to the results of the post-layout simulation with a similar power supply of 2.0 V. The chip area for the proposed layout design is 1.05 mm2.
      1