Phak Len Al Eh Kan
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Phak Len Al Eh Kan
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Phak, Len Al Eh Kan
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Ehkan, Phaklen
Kan, P. L.Eh
Ehkan, Phak Len
Ehkan, P. L.
Eh Kan, P.
Eh Kan, P.
Al Eh Kan, Phak Len
Eh Kan, Phaklen
Kan, P. Eh
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37005452000

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  • Publication
    Multipoint Relay Path for Efficient Topology Maintenance Algorithm in Optimized Link State Routing-Based for VANET
    ( 2024-01-01)
    Waleed Khalid Ahmed
    ;
    Mohd Nazri Mohd Warip
    ;
    Mohamed Elshaikh Elobaid Said Ahmed
    ;
    Phak Len Al Eh Kan
    The Optimal Link State Routing (OLSR) protocol employs multipoint relay (MPR) nodes to disseminate topology control (TC) messages, enabling network topology discovery and maintenance. However, this approach increases control overhead and leads to wasted network bandwidth in stable topology scenarios due to fixed flooding periods. To address these challenges, this paper presents an Efficient Topology Maintenance Algorithm (ETM-OLSR) for Enhanced Link-State Routing Protocols. By reducing the number of MPR nodes, TC message generation and forwarding frequency are minimized. Furthermore, the algorithm selects a smaller subset of TC messages based on the changes in the MPR selection set from the previous cycle, adapting to stable and fluctuating network conditions. Additionally, the sending cycle of TC messages is dynamically adjusted in response to network topology changes. Simulation results demonstrate that the ETM-OLSR algorithm effectively reduces network control overhead, minimizes end-to-end delay, and improves network throughput compared to traditional OLSR and HTR-OLSR algorithms.
  • Publication
    Imporved MPR selection algorithm-based WS-OLSR routing protocol
    ( 2024-05-01)
    Ahmed W.K.
    ;
    Mohd Nazri Mohd Warip
    ;
    Mohamed Elshaikh Elobaid Said Ahmed
    ;
    Phak Len Al Eh Kan
    Vehicle Ad Hoc Networks (VANETs) have become a viable technology to improve traffic flow and safety on the roads. Due to its effectiveness and scalability, the Wingsuit Search-based Optimised Link State Routing Protocol (WS-OLSR) is frequently used for data distribution in VANETs. However, the selection of MultiPoint Relays (MPRs) plays a pivotal role in WS-OLSR’s performance. This paper presents an improved MPR selection algorithm tailored to WS-OLSR, designed to enhance the overall routing efficiency and reduce overhead. The analysis found that the current OLSR protocol has problems such as redundancy of HELLO and TC message packets or failure to update routing information in time, so a WS-OLSR routing protocol based on improved-MPR selection algorithm was proposed. Firstly, factors such as node mobility and link changes are comprehensively considered to reflect network topology changes, and the broadcast cycle of node HELLO messages is controlled through topology changes. Secondly, a new MPR selection algorithm is proposed, considering link stability issues and nodes. Finally, evaluate its effectiveness in terms of packet delivery ratio, end-to-end delay, and control message overhead. Simulation results demonstrate the superior performance of our improved MR selection algorithm when compared to traditional approaches.
      1
  • Publication
    Deep Learning with FPGA: Age and Gender Recognition for Smart Advertisement Board
    ( 2023-10-06)
    Yeoh W.S.
    ;
    Fazrul Faiz Zakaria
    ;
    Mustapa M.
    ;
    Mohd Nazri Mohd Warip
    ;
    Phak Len Al Eh Kan
    ;
    Mozi A.M.
    Age and gender recognition are helpful in various applications, especially in the field of advertising. To replace the traditional advertising method that can only display the same contents to all audiences, a smart advertisement board capable of detecting age and gender of audiences to display relevant contents is required to increase the effectiveness of advertising. This paper will use two image datasets to train and test the Convolutional Neural Network (CNN) based architecture models for age and gender recognition using deep learning. The dataset that produced the best performing model will be implemented on three different devices to observe the performance of the models on each device. A gender recognition model with accuracy of 91.53% and age recognition model with accuracy of 59.62% is produced. The results have also shown the use of Field Programmable Gated Array (FPGA) has greatly boosted the performance of the models in terms of throughput and latency.
      1
  • Publication
    Improving Energy Detection Performance Using Segment of Primary User Signal Energy in Wide-band Cognitive Radio Systems
    ( 2023-10-06)
    BaAli K.
    ;
    Abo-Zahhad M.
    ;
    Farrag M.
    ;
    Ahmed S.
    ;
    Phak Len Al Eh Kan
    Energy detection based cognitive radio has gained remarkable attention. This is because of its simple implementation and it does not involve any prior knowledge of the detecting signal. Although, it is prone to noise uncertainty. Recently, the use of compressed measurements improved the performance of energy detection. In this paper, we investigate the effect of using a segment of primary user signal energy ƞE on detection performance regarding compression ratios. The simulation results show the detector performance becomes better as ƞE increased. However, increasing ƞE should be bounded, so it does not involve sacrificing the use of the compressed measurement system as a suggestion to improve energy detection performance.
      1
  • Publication
    Received signal strength indication (RSSI) code assessment for wireless sensors network (WSN) deployed Raspberry-Pi
    ( 2017-03-06)
    Mohd Ilman Jais
    ;
    Thennarasan Sabapathy
    ;
    Muzammil Jusoh
    ;
    Phak Len Al Eh Kan
    ;
    Murukesan L.
    ;
    Ismail I.
    ;
    R Badlishah Ahmad
    Wireless sensor network (WSN) is commonly used for localization applications. Through sniffing receive signal strength indicator (RSSI) in WSN system, localization and connection to access point highest RSSI can be done automatically. In this paper, we propose Raspberry-Pi (RasPi), based best access point selection method utilizing RSSI metric. The RasPi brings the advantages of a personal computer (PC) to the domain of sensor network, which makes it the perfect platform for interfacing with a wide variety of external peripherals. This work aims to investigate various source codes deployed on RasPi for localization purpose by sniffing the RSSI metric. Consequently, comparative analysis of its key elements and performances with some of the currently available wireless sensor nodes have shown that despite few disadvantages, RasPi remains an inexpensive single board computer (SBC) which has been used very successfully in sensor network domain and diverse range of research applications.
  • Publication
    Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture
    ( 2017-06-01)
    Ng Yen Phing
    ;
    Mohd Nazri Mohd Warip
    ;
    Phak Len Al Eh Kan
    ;
    Farah W. Zulkefli
    ;
    R Badlishah Ahmad
    In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as a design solution to System-on-Chip (SoC). The routing algorithm, topology and switching technique are significant because of the most influential effect on the overall performance of Network-on-Chip (NoC). Designing of large scale topology alongside the support of deadlock free, low latency, high throughput and low power consumption is notably challenging in particular with expanding network size. This paper proposed an 8x8 XX-Torus and 64 nodes XX-Ring topology schemes for Network-on-Chip to minimize the latency by decrease the node diameter from the source node to destination node. Correspondingly, we compare in differences on the performance of mesh, full-mesh, torus and ring topologies with XX-Torus and XX-Ring topologies in term of latency. Results show that XX-Ring outperforms the conventional topologies in term of latency. XX-Ring decreases the average latency by 106.28%, 14.80%, 6.7 1%, 1.73%, 442.24% over the mesh, fully-mesh, torus, XX-torus, and Ring topologies.
  • Publication
    Implementation of image file security using the advanced encryption standard method
    ( 2023-07-01)
    Ikhwan A.
    ;
    Rafikha Aliana A Raof
    ;
    Phak Len Al Eh Kan
    ;
    Yasmin Mohd Yacob
    ;
    Aslami N.
    The application of technology in this era has entered digitalization and is modern. Therefore, we are already in an era of advanced and rapid technological development. It has become a human need to exchange information in every activity. Documents that contain information that is frequently sought or used. The document's use also includes essential information. Document security is undoubtedly a significant factor in prioritizing important information in a document to prevent unauthorized people from misusing the document's vital information. Cryptography is a method of overcoming document security issues so that third parties cannot read the information or messages contained within the document. The 128-bit advanced encryption standard (AES) algorithm is one of the algorithms included in the cryptography technique. Additionally, it can be combined with operation modes such as electronic codebook (ECB) and cipher block chaining (CBC) to create an application that can generate random codes to improve the security of the data contained in the document.
      1
  • Publication
    Breast cancer classification using deep learning and FPGA inferencing
    ( 2023-02-21)
    Wong E.H.
    ;
    Fazrul Faiz Zakaria
    ;
    Mustapa M.
    ;
    Mohd Nazri Mohd Warip
    ;
    Phak Len Al Eh Kan
    Implementing deep learning technology with FPGA as an accelerator has become a popular application due to its efficiency and performance. However, given the tremendous data generated on medical diagnosis, normal inference speed is not sufficient. Hence, the FPGA technology is implemented for fast inference. In this context, the FPGA accelerates the deep learning inference process for fast breast cancer classification with minimal latency on real-time deployment. This paper summarizes the findings of model deployment across various computing devices in deep learning technology with FPGA. The study includes model performance evaluation, throughput, and latency comparison with different batch sizes to the extent of expected delay for real-world deployment. The result concludes that FPGA is the most suitable to act as a deep learning inference accelerator with a high throughput-to-latency ratio and fast parallel inference.
      1
  • Publication
    FPGA Implementation of High-Capacity SD Card using VHDL Language
    ( 2024-01-01)
    Taha T.B.
    ;
    Ruzelita Ngadiran
    ;
    Phak Len Al Eh Kan
    Limitations in capacity of internal memory chips on embedded systems lead to the usage of external memories especially when processing large amount of data as images or videos. FPGAs as embedded system devices used in different signal processing applications require extra memory for data storage. Current attempts in programming Secure Digital (SD) cards as external memories attached to FPGAs came with utilization of aiding application or of shelf tools which consumes large amount of chip clock cycles and reduce the overall performance. In this paper, a hardware implementation of SD card programming is presented by using pure and standalone VHDL code with high programming flexibility. In addition, High-Capacity SD cards (SDHC) are implemented for maximum storage capacity to handle large amount of data.
      1